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Searched refs:DestSub0 (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp2722 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
2723 BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitUnaryOp()
2735 .addReg(DestSub0) in splitScalar64BitUnaryOp()
2783 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitBinaryOp() local
2784 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
2800 .addReg(DestSub0) in splitScalar64BitBinaryOp()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp4202 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
4203 BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp()
4213 .addReg(DestSub0) in splitScalar64BitUnaryOp()
4235 unsigned DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitAddSub() local
4265 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0) in splitScalar64BitAddSub()
4279 .addReg(DestSub0) in splitScalar64BitAddSub()
4329 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitBinaryOp() local
4330 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
4346 .addReg(DestSub0) in splitScalar64BitBinaryOp()
DSIISelLowering.cpp3256 unsigned DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in EmitInstrWithCustomInserter() local
3277 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) in EmitInstrWithCustomInserter()
3284 .addReg(DestSub0) in EmitInstrWithCustomInserter()