| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 105 const MachineOperand &DstOp = MI->getOperand(0); in interpretAsCopy() local
108 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in interpretAsCopy()
109 mapRegs({ DstOp.getReg(), Hexagon::subreg_hireg }, in interpretAsCopy()
111 mapRegs({ DstOp.getReg(), Hexagon::subreg_loreg }, in interpretAsCopy()
122 const MachineOperand &DstOp = MI->getOperand(0); in interpretAsCopy() local
124 mapRegs({ DstOp.getReg(), DstOp.getSubReg() }, in interpretAsCopy()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 121 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi), in INITIALIZE_PASS_DEPENDENCY()
127 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo), in INITIALIZE_PASS_DEPENDENCY()
138 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 101 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction() local
103 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
104 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1155 static std::string getShuffleComment(const MachineOperand &DstOp, in getShuffleComment() argument
1171 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; in getShuffleComment()
1466 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
1474 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1488 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
1496 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1510 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
1518 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1531 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
1551 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); in EmitInstruction()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Linker/ |
| D | IRMover.cpp | 1157 MDNode *DstOp; in linkModuleFlagsMetadata() local
1159 std::tie(DstOp, DstIndex) = Flags.lookup(ID); in linkModuleFlagsMetadata()
1173 if (!DstOp) { in linkModuleFlagsMetadata()
1181 mdconst::extract<ConstantInt>(DstOp->getOperand(0)); in linkModuleFlagsMetadata()
1193 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1209 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New}; in linkModuleFlagsMetadata()
1222 if (SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1229 if (SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1237 mdconst::extract<ConstantInt>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
1245 MDNode *DstValue = cast<MDNode>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
[all …]
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| /external/llvm/lib/Linker/ |
| D | IRMover.cpp | 1049 MDNode *DstOp; in linkModuleFlagsMetadata() local
1051 std::tie(DstOp, DstIndex) = Flags.lookup(ID); in linkModuleFlagsMetadata()
1065 if (!DstOp) { in linkModuleFlagsMetadata()
1073 mdconst::extract<ConstantInt>(DstOp->getOperand(0)); in linkModuleFlagsMetadata()
1080 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1097 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New}; in linkModuleFlagsMetadata()
1110 if (SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1117 if (SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1124 MDNode *DstValue = cast<MDNode>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
1136 MDNode *DstValue = cast<MDNode>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 85 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction() local
87 DstOp.getReg(), AMDGPU::OQAP); in runOnMachineFunction()
88 DstOp.setReg(AMDGPU::OQAP); in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrFoldTables.h | 58 uint16_t DstOp; member
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| D | X86MCInstLower.cpp | 1446 const MachineOperand &DstOp = MI->getOperand(0); in getShuffleComment() local
1450 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; in getShuffleComment()
2041 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
2042 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in EmitInstruction()
2122 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
2123 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in EmitInstruction()
2226 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
2227 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in EmitInstruction()
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| D | X86InstrInfo.cpp | 4899 unsigned Opcode = I->DstOp; in foldMemoryOperandImpl()
5362 unsigned Opc = I->DstOp; in unfoldMemoryOperand()
5484 unsigned Opc = I->DstOp; in unfoldMemoryOperand()
5623 return I->DstOp; in getOpcodeAfterMemoryUnfold()
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| D | X86InstrFoldTables.cpp | 5396 Table.push_back({Entry.DstOp, Entry.KeyOp, in addTableEntry()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineVerifier.cpp | 1044 const MachineOperand &DstOp = MI->getOperand(0); in visitMachineInstrBefore() local
1046 LLT DstTy = MRI->getType(DstOp.getReg()); in visitMachineInstrBefore()
1059 unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI); in visitMachineInstrBefore()
1063 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) { in visitMachineInstrBefore()
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| D | MachineScheduler.cpp | 1677 const MachineOperand &DstOp = Copy->getOperand(0); in constrainLocalCopy() local
1678 unsigned DstReg = DstOp.getReg(); in constrainLocalCopy()
1679 if (!TargetRegisterInfo::isVirtualRegister(DstReg) || DstOp.isDead()) in constrainLocalCopy()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | GlobalISelEmitter.cpp | 3685 Record *DstOp = Dst->getOperator(); in createInstructionRenderer() local
3686 if (!DstOp->isSubClassOf("Instruction")) { in createInstructionRenderer()
3687 if (DstOp->isSubClassOf("ValueType")) in createInstructionRenderer()
3692 CodeGenInstruction *DstI = &Target.getInstruction(DstOp); in createInstructionRenderer()
3919 Record *DstOp = Dst->getOperator(); in runOnPattern() local
3920 if (!DstOp->isSubClassOf("Instruction")) in runOnPattern()
3923 auto &DstI = Target.getInstruction(DstOp); in runOnPattern()
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| /external/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 1604 const MachineOperand &DstOp = Copy->getOperand(0); in constrainLocalCopy() local
1605 unsigned DstReg = DstOp.getReg(); in constrainLocalCopy()
1606 if (!TargetRegisterInfo::isVirtualRegister(DstReg) || DstOp.isDead()) in constrainLocalCopy()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 7540 bit WithStride, DAGOperand DstOp>
7553 dag InsR03 = (ins DstOp:$src, regclass:$r0, regclass:$r1,
|