Searched refs:ESW_SYS_DIV_ADDR (Results 1 – 2 of 2) sorted by relevance
25 #define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04) macro80 writel((readl(ESW_SYS_DIV_ADDR) & in clk_eth_enable()83 ESW_SYS_DIV_ADDR); in clk_eth_enable()85 writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, in clk_eth_enable()86 ESW_SYS_DIV_ADDR); in clk_eth_enable()93 if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { in clk_eth_enable()