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Searched refs:FCVTZU (Results 1 – 10 of 10) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-basic-a64-undefined.txt27 # Same with FCVTZS and FCVTZU.
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-basic-a64-undefined.txt27 # Same with FCVTZS and FCVTZU.
/external/vixl/src/aarch64/
Dconstants-aarch64.h1497 FCVTZU = FPIntegerConvertFixed | 0x00190000, enumerator
1498 FCVTZU_wh = FCVTZU | FP16,
1499 FCVTZU_xh = FCVTZU | SixtyFourBits | FP16,
1500 FCVTZU_ws = FCVTZU,
1501 FCVTZU_xs = FCVTZU | SixtyFourBits,
1502 FCVTZU_wd = FCVTZU | FP64,
1503 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
Ddisasm-aarch64.cc2487 FORMAT(FCVTZU, "fcvtzu") in VisitNEON2RegMiscFP16()
3980 FORMAT(FCVTZU, "fcvtzu") in VisitNEONScalar2RegMiscFP16()
Dassembler-aarch64.cc3021 Emit(SF(rd) | FPType(vn) | FCVTZU | Rn(vn) | Rd(rd)); in fcvtzu()
/external/v8/src/arm64/
Dconstants-arm64.h1276 FCVTZU = FPIntegerConvertFixed | 0x00190000, enumerator
1277 FCVTZU_ws = FCVTZU,
1278 FCVTZU_xs = FCVTZU | SixtyFourBits,
1279 FCVTZU_wd = FCVTZU | FP64,
1280 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
Dassembler-arm64.cc3374 Emit(SF(rd) | FPType(vn) | FCVTZU | Rn(vn) | Rd(rd)); in fcvtzu()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2502 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2504 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2529 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;
2547 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
2820 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
3360 defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">;
4679 defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">;
4753 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2783 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2785 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2810 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;
2828 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
3084 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
3637 defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">;
5014 defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">;
5123 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md1992 ### FCVTZU ### subsection
1999 ### FCVTZU ### subsection