| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 535 FMINNAN, FMAXNAN, enumerator
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| D | BasicTTIImpl.h | 771 ISDs.push_back(ISD::FMINNAN); in getIntrinsicInstrCost()
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| D | SelectionDAG.h | 1188 case ISD::FMINNAN:
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 568 FMINNAN, FMAXNAN, enumerator
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| D | BasicTTIImpl.h | 1042 ISDs.push_back(ISD::FMINNAN);
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| D | TargetLowering.h | 2051 case ISD::FMINNAN: in isCommutativeBinOp()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 155 case ISD::FMINNAN: return "fminnan"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 305 case ISD::FMINNAN: in LegalizeOp()
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| D | SelectionDAGBuilder.cpp | 2784 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break; in visitSelect()
2789 else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT)) in visitSelect()
2790 Opc = ISD::FMINNAN; in visitSelect()
2793 ISD::FMINNUM : ISD::FMINNAN; in visitSelect()
5209 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT) in visitIntrinsicCall()
5210 ? ISD::FMINNAN in visitIntrinsicCall()
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| D | LegalizeVectorTypes.cpp | 112 case ISD::FMINNAN: in ScalarizeVectorResult()
677 case ISD::FMINNAN: in SplitVectorResult()
2093 case ISD::FMINNAN: in WidenVectorResult()
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| D | LegalizeFloatTypes.cpp | 1890 case ISD::FMINNAN: in PromoteFloatResult()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 178 case ISD::FMINNAN: return "fminnan"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 116 case ISD::FMINNAN: in ScalarizeVectorResult()
734 case ISD::FMINNAN: in SplitVectorResult()
1752 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINNAN; in SplitVecOp_VECREDUCE()
2301 case ISD::FMINNAN: in WidenVectorResult()
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| D | LegalizeVectorOps.cpp | 364 case ISD::FMINNAN: in LegalizeOp()
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| D | SelectionDAGBuilder.cpp | 2963 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break; in visitSelect()
2968 else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT)) in visitSelect()
2969 Opc = ISD::FMINNAN; in visitSelect()
2972 ISD::FMINNUM : ISD::FMINNAN; in visitSelect()
5556 I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT) in visitIntrinsicCall()
5557 ? ISD::FMINNAN in visitIntrinsicCall()
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| D | LegalizeFloatTypes.cpp | 1909 case ISD::FMINNAN: in PromoteFloatResult()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 90 setOperationAction(ISD::FMINNAN, T, Legal); in WebAssemblyTargetLowering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 97 setOperationAction(ISD::FMINNAN, T, Legal); in WebAssemblyTargetLowering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 457 setOperationAction(ISD::FMINNAN, MVT::f64, Legal); in SystemZTargetLowering()
462 setOperationAction(ISD::FMINNAN, MVT::v2f64, Legal); in SystemZTargetLowering()
467 setOperationAction(ISD::FMINNAN, MVT::f32, Legal); in SystemZTargetLowering()
472 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal); in SystemZTargetLowering()
477 setOperationAction(ISD::FMINNAN, MVT::f128, Legal); in SystemZTargetLowering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 602 setOperationAction(ISD::FMINNAN, VT, Expand); in initActions()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 870 setOperationAction(ISD::FMINNAN, VT, Expand); in initActions()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 437 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 388 setOperationAction(ISD::FMINNAN, MVT::f16, Promote); in AArch64TargetLowering()
453 setOperationAction(ISD::FMINNAN, Ty, Legal); in AArch64TargetLowering()
466 setOperationAction(ISD::FMINNAN, MVT::f16, Legal); in AArch64TargetLowering()
819 for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN, in addTypeForNEON()
9723 return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 419 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 294 setOperationAction(ISD::FMINNAN, MVT::f16, Promote); in AArch64TargetLowering()
386 setOperationAction(ISD::FMINNAN, Ty, Legal); in AArch64TargetLowering()
704 for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN, in addTypeForNEON()
8558 return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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