| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2111 ISD = ISD::FMINNUM; in getMinMaxReductionCost()
2118 {ISD::FMINNUM, MVT::v2f64, 3}, in getMinMaxReductionCost()
2119 {ISD::FMINNUM, MVT::v4f32, 2}, in getMinMaxReductionCost()
2129 {ISD::FMINNUM, MVT::v4f32, 1}, in getMinMaxReductionCost()
2130 {ISD::FMINNUM, MVT::v4f64, 1}, in getMinMaxReductionCost()
2131 {ISD::FMINNUM, MVT::v8f32, 2}, in getMinMaxReductionCost()
2154 {ISD::FMINNUM, MVT::v8f64, 1}, in getMinMaxReductionCost()
2155 {ISD::FMINNUM, MVT::v16f32, 2}, in getMinMaxReductionCost()
2163 {ISD::FMINNUM, MVT::v2f64, 3}, in getMinMaxReductionCost()
2164 {ISD::FMINNUM, MVT::v4f32, 3}, in getMinMaxReductionCost()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 532 FMINNUM, FMAXNUM, enumerator
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| D | BasicTTIImpl.h | 769 ISDs.push_back(ISD::FMINNUM); in getIntrinsicInstrCost()
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| D | SelectionDAG.h | 1186 case ISD::FMINNUM:
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 565 FMINNUM, FMAXNUM, enumerator
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| D | BasicTTIImpl.h | 1040 ISDs.push_back(ISD::FMINNUM);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 334 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; in mightUseCTR()
400 Opcode = ISD::FMINNUM; break; in mightUseCTR()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 308 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; in mightUseCTR()
372 Opcode = ISD::FMINNUM; break; in mightUseCTR()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 205 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SITargetLowering()
223 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
1709 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
2699 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc()
2816 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) || in performMinMaxCombine()
2869 case ISD::FMINNUM: in PerformDAGCombine()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 153 case ISD::FMINNUM: return "fminnum"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 77 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
1017 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break; in ExpandFloatResult()
1892 case ISD::FMINNUM: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 303 case ISD::FMINNUM: in LegalizeOp()
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| D | SelectionDAGBuilder.cpp | 2785 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; in visitSelect()
2787 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT)) in visitSelect()
2788 Opc = ISD::FMINNUM; in visitSelect()
2792 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ? in visitSelect()
2793 ISD::FMINNUM : ISD::FMINNAN; in visitSelect()
5211 : ISD::FMINNUM; in visitIntrinsicCall()
6249 if (visitBinaryFloatCall(I, ISD::FMINNUM)) in visitCall()
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| D | LegalizeVectorTypes.cpp | 110 case ISD::FMINNUM: in ScalarizeVectorResult()
675 case ISD::FMINNUM: in SplitVectorResult()
2091 case ISD::FMINNUM: in WidenVectorResult()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 378 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SITargetLowering()
469 setOperationAction(ISD::FMINNUM, MVT::f16, Legal); in SITargetLowering()
569 setOperationAction(ISD::FMINNUM, MVT::v2f16, Legal); in SITargetLowering()
590 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom); in SITargetLowering()
624 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
3642 case ISD::FMINNUM: in LowerOperation()
4812 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
6718 case ISD::FMINNUM: in fp16SrcZerosHighBits()
6851 case ISD::FMINNUM: in isCanonicalized()
6951 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc()
[all …]
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| D | AMDGPUISelLowering.cpp | 313 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
446 setOperationAction(ISD::FMINNUM, VT, Expand); in AMDGPUTargetLowering()
551 case ISD::FMINNUM: in fnegFoldsIntoOp()
3461 return ISD::FMINNUM; in inverseMinMax()
3462 case ISD::FMINNUM: in inverseMinMax()
3568 case ISD::FMINNUM: in performFNegCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 176 case ISD::FMINNUM: return "fminnum"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 77 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
1071 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break; in ExpandFloatResult()
1911 case ISD::FMINNUM: in PromoteFloatResult()
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| D | LegalizeVectorTypes.cpp | 114 case ISD::FMINNUM: in ScalarizeVectorResult()
732 case ISD::FMINNUM: in SplitVectorResult()
1752 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINNAN; in SplitVecOp_VECREDUCE()
2299 case ISD::FMINNUM: in WidenVectorResult()
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| D | LegalizeVectorOps.cpp | 362 case ISD::FMINNUM: in LegalizeOp()
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| D | SelectionDAGBuilder.cpp | 2964 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; in visitSelect()
2966 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT)) in visitSelect()
2967 Opc = ISD::FMINNUM; in visitSelect()
2971 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ? in visitSelect()
2972 ISD::FMINNUM : ISD::FMINNAN; in visitSelect()
5558 : ISD::FMINNUM; in visitIntrinsicCall()
6905 if (visitBinaryFloatCall(I, ISD::FMINNUM)) in visitCall()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 115 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in RISCVTargetLowering()
125 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in RISCVTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 292 setOperationAction(ISD::FMINNUM, MVT::f16, Promote); in AArch64TargetLowering()
384 setOperationAction(ISD::FMINNUM, Ty, Legal); in AArch64TargetLowering()
705 ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON()
8564 return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
8952 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in tryMatchAcrossLaneShuffleForReduction()
9033 case ISD::FMINNUM: in tryMatchAcrossLaneShuffleForReduction()
9098 Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM) in performAcrossLaneMinMaxReductionCombine()
9109 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in performAcrossLaneMinMaxReductionCombine()
9136 (Op == ISD::FMINNUM && CC != ISD::SETOLT && CC != ISD::SETOLE && in performAcrossLaneMinMaxReductionCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 456 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SystemZTargetLowering()
461 setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
466 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in SystemZTargetLowering()
471 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
476 setOperationAction(ISD::FMINNUM, MVT::f128, Legal); in SystemZTargetLowering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 600 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
|