| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 1518 X86_INTRINSIC_DATA(avx512_mask_vfnmsub_pd_128, FMA_OP_MASK, X86ISD::FNMSUB, 0),
1519 X86_INTRINSIC_DATA(avx512_mask_vfnmsub_pd_256, FMA_OP_MASK, X86ISD::FNMSUB, 0),
1520 X86_INTRINSIC_DATA(avx512_mask_vfnmsub_pd_512, FMA_OP_MASK, X86ISD::FNMSUB,
1522 X86_INTRINSIC_DATA(avx512_mask_vfnmsub_ps_128, FMA_OP_MASK, X86ISD::FNMSUB, 0),
1523 X86_INTRINSIC_DATA(avx512_mask_vfnmsub_ps_256, FMA_OP_MASK, X86ISD::FNMSUB, 0),
1524 X86_INTRINSIC_DATA(avx512_mask_vfnmsub_ps_512, FMA_OP_MASK, X86ISD::FNMSUB,
1667 X86_INTRINSIC_DATA(avx512_mask3_vfnmsub_pd_128, FMA_OP_MASK3, X86ISD::FNMSUB, 0),
1668 X86_INTRINSIC_DATA(avx512_mask3_vfnmsub_pd_256, FMA_OP_MASK3, X86ISD::FNMSUB, 0),
1669 X86_INTRINSIC_DATA(avx512_mask3_vfnmsub_pd_512, FMA_OP_MASK3, X86ISD::FNMSUB,
1671 X86_INTRINSIC_DATA(avx512_mask3_vfnmsub_ps_128, FMA_OP_MASK3, X86ISD::FNMSUB, 0),
[all …]
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| D | X86ISelLowering.h | 477 FNMSUB, enumerator
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| D | X86InstrFragmentsSIMD.td | 472 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
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| D | X86ISelLowering.cpp | 22287 case X86ISD::FNMSUB: return "X86ISD::FNMSUB"; in getTargetNodeName()
29751 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0), in combineFneg()
29760 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0), in combineFneg()
29768 case X86ISD::FNMSUB: in combineFneg()
30231 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB; in combineFMA()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 490 FNMSUB, enumerator
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| D | X86InstrFragmentsSIMD.td | 473 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
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| D | X86ISelLowering.cpp | 26111 case X86ISD::FNMSUB: return "X86ISD::FNMSUB"; in getTargetNodeName()
37002 SDValue NewNode = DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0), in combineFneg()
37012 case ISD::FMA: NewOpcode = X86ISD::FNMSUB; break; in combineFneg()
37015 case X86ISD::FNMSUB: NewOpcode = ISD::FMA; break; in combineFneg()
37879 case X86ISD::FMSUB: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
37883 case X86ISD::FNMSUB: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
37895 case X86ISD::FNMADD: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
37897 case X86ISD::FNMSUB: Opcode = X86ISD::FNMADD; break; in negateFMAOpcode()
39733 case X86ISD::FNMSUB: in PerformDAGCombine()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 1261 def FNMSUB : AForm_1<63, 30,
1431 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
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| /external/v8/src/ppc/ |
| D | constants-ppc.h | 1862 V(fnmsub, FNMSUB, 0xFC00003C) \
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 425 FNMSUB,
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| D | PPCInstrInfo.td | 2839 defm FNMSUB : AForm_1r<63, 30,
3155 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
3157 (FNMSUB $A, $C, $B)>;
3159 (FNMSUB $A, $C, $B)>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 2559 defm FNMSUB : AForm_1r<63, 30,
2872 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2874 (FNMSUB $A, $C, $B)>;
2876 (FNMSUB $A, $C, $B)>;
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| /external/v8/src/arm64/ |
| D | disasm-arm64.cc | 1087 FORMAT(FNMSUB, "fnmsub"); in VisitFPDataProcessing3Source()
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| /external/vixl/src/aarch64/ |
| D | disasm-aarch64.cc | 1753 FORMAT(FNMSUB, "fnmsub"); in VisitFPDataProcessing3Source()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX2T99.td | 1182 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
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| D | AArch64InstrInfo.td | 2925 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2279 ### FNMSUB ### subsection
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| /external/capstone/arch/PowerPC/ |
| D | PPCGenDisassemblerTables.inc | 2227 /* 9344 */ MCD_OPC_Decode, 144, 4, 112, // Opcode: FNMSUB
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| D | PPCGenAsmWriter.inc | 548 18517U, // FNMSUB
1821 40U, // FNMSUB
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2637 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
|