Searched refs:FPZero (Results 1 – 8 of 8) sorted by relevance
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 2918 WriteWRegister(dst, FPToInt32(ReadHRegister(src), FPZero)); in VisitFPIntegerConvert()
2921 WriteXRegister(dst, FPToInt64(ReadHRegister(src), FPZero)); in VisitFPIntegerConvert()
2924 WriteWRegister(dst, FPToInt32(ReadSRegister(src), FPZero)); in VisitFPIntegerConvert()
2927 WriteXRegister(dst, FPToInt64(ReadSRegister(src), FPZero)); in VisitFPIntegerConvert()
2930 WriteWRegister(dst, FPToInt32(ReadDRegister(src), FPZero)); in VisitFPIntegerConvert()
2933 WriteXRegister(dst, FPToInt64(ReadDRegister(src), FPZero)); in VisitFPIntegerConvert()
2936 WriteWRegister(dst, FPToUInt32(ReadHRegister(src), FPZero)); in VisitFPIntegerConvert()
2939 WriteXRegister(dst, FPToUInt64(ReadHRegister(src), FPZero)); in VisitFPIntegerConvert()
2942 WriteWRegister(dst, FPToUInt32(ReadSRegister(src), FPZero)); in VisitFPIntegerConvert()
2945 WriteXRegister(dst, FPToUInt64(ReadSRegister(src), FPZero)); in VisitFPIntegerConvert()
[all …]
|
| D | logic-aarch64.cc | 4048 case FPZero: { in FPRoundInt()
5075 case FPZero: in FPRecipEstimate()
|
| /external/v8/src/arm64/ |
| D | simulator-arm64.cc | 2584 case FCVTZS_ws: set_wreg(dst, FPToInt32(sreg(src), FPZero)); break; in VisitFPIntegerConvert()
2585 case FCVTZS_xs: set_xreg(dst, FPToInt64(sreg(src), FPZero)); break; in VisitFPIntegerConvert()
2586 case FCVTZS_wd: set_wreg(dst, FPToInt32(dreg(src), FPZero)); break; in VisitFPIntegerConvert()
2587 case FCVTZS_xd: set_xreg(dst, FPToInt64(dreg(src), FPZero)); break; in VisitFPIntegerConvert()
2588 case FCVTZU_ws: set_wreg(dst, FPToUInt32(sreg(src), FPZero)); break; in VisitFPIntegerConvert()
2589 case FCVTZU_xs: set_xreg(dst, FPToUInt64(sreg(src), FPZero)); break; in VisitFPIntegerConvert()
2590 case FCVTZU_wd: set_wreg(dst, FPToUInt32(dreg(src), FPZero)); break; in VisitFPIntegerConvert()
2591 case FCVTZU_xd: set_xreg(dst, FPToUInt64(dreg(src), FPZero)); break; in VisitFPIntegerConvert()
2810 fpcr_rounding = FPZero; in VisitFPDataProcessing1Source()
3610 fpcr_rounding = FPZero; in VisitNEON2RegMisc()
[all …]
|
| D | instructions-arm64.h | 64 FPZero = 0x3, enumerator
|
| D | simulator-logic-arm64.cc | 3189 case FPZero: { in FPRoundInt()
3977 case FPZero: in FPRecipEstimate()
|
| /external/vixl/src/ |
| D | utils-vixl.h | 1009 FPZero = 0x3, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 18332 SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); in buildSqrtEstimateImpl() local
18335 Est = DAG.getNode(SelOpcode, DL, VT, IsDenorm, FPZero, Est); in buildSqrtEstimateImpl()
18341 SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); in buildSqrtEstimateImpl() local
18342 SDValue IsZero = DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); in buildSqrtEstimateImpl()
18343 Est = DAG.getNode(SelOpcode, DL, VT, IsZero, FPZero, Est); in buildSqrtEstimateImpl()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 5300 SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); in getSqrtEstimate() local
5301 SDValue Eq = DAG.getSetCC(DL, CCVT, Operand, FPZero, ISD::SETEQ); in getSqrtEstimate()
|