Home
last modified time | relevance | path

Searched refs:FP_EXTEND (Results 1 – 25 of 70) sorted by relevance

123

/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h416 FP_EXTEND, enumerator
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp84 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
85 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
89 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h480 FP_EXTEND, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp640 case ISD::FP_EXTEND: in isNegatibleForFree()
716 case ISD::FP_EXTEND: in GetNegatedExpression()
1418 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
7819 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7823 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7825 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7831 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7835 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7837 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7873 DAG.getNode(ISD::FP_EXTEND, SL, VT, U), in visitFADDForFMACombine()
[all …]
DLegalizeFloatTypes.cpp94 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
460 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
658 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
756 case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break; in SoftenFloatOperand()
1034 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1271 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
1749 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
1800 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
2131 ISD::FP_EXTEND, DL, NVT, in PromoteFloatRes_XINT_TO_FP()
DLegalizeDAG.cpp2325 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in ExpandLegalINT_TO_FP()
2890 case ISD::FP_EXTEND: in ExpandNode()
3176 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
4122 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4153 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4166 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4187 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4188 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4196 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4197 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
DLegalizeVectorOps.cpp325 case ISD::FP_EXTEND: in LegalizeOp()
416 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); in Promote()
DSelectionDAGDumper.cpp252 case ISD::FP_EXTEND: return "fp_extend"; in getOperationName()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp145 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
146 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
150 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h526 FP_EXTEND, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp94 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
463 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
659 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
761 case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break; in SoftenFloatOperand()
1088 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1325 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
1766 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
1818 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
2155 ISD::FP_EXTEND, DL, NVT, in PromoteFloatRes_XINT_TO_FP()
DDAGCombiner.cpp688 if (!(Op.getOpcode() == ISD::FP_EXTEND && in isNegatibleForFree()
740 case ISD::FP_EXTEND: in isNegatibleForFree()
807 case ISD::FP_EXTEND: in GetNegatedExpression()
1573 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
8219 CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || in matchVSelectOpSizesWithSetCC()
10182 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
10187 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
10189 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
10196 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
10201 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
[all …]
DLegalizeDAG.cpp2358 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in ExpandLegalINT_TO_FP()
2985 case ISD::FP_EXTEND: in ExpandNode()
3283 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
4450 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4481 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4494 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4515 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4516 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4523 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4524 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
DLegalizeVectorOps.cpp384 case ISD::FP_EXTEND: in LegalizeOp()
488 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); in Promote()
DSelectionDAGDumper.cpp295 case ISD::FP_EXTEND: return "fp_extend"; in getOperationName()
DLegalizeVectorTypes.cpp91 case ISD::FP_EXTEND: in ScalarizeVectorResult()
544 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res) in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
702 case ISD::FP_EXTEND: in SplitVectorResult()
1640 case ISD::FP_EXTEND: in SplitVectorOperand()
2344 case ISD::FP_EXTEND: in WidenVectorResult()
3427 case ISD::FP_EXTEND: in WidenVectorOperand()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp554 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, in getCastInstrCost()
555 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
641 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, in getCastInstrCost()
719 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, in getCastInstrCost()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp82 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
499 return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL)); in SoftenFloatRes_LOAD()
865 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1062 Hi = DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
DLegalizeVectorTypes.cpp82 case ISD::FP_EXTEND: in ScalarizeVectorResult()
458 case ISD::FP_EXTEND: in SplitVectorResult()
984 case ISD::FP_EXTEND: in SplitVectorOperand()
1283 case ISD::FP_EXTEND: in WidenVectorResult()
2036 case ISD::FP_EXTEND: in WidenVectorOperand()
DLegalizeDAG.cpp513 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); in ExpandUnalignedLoad()
1360 ISD::FP_EXTEND : ISD::ANY_EXTEND); in LegalizeOp()
2510 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in ExpandLegalINT_TO_FP()
3098 case ISD::FP_EXTEND: in ExpandNode()
3909 ExtOp = ISD::FP_EXTEND; in PromoteNode()
3941 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp230 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
396 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); in AArch64TargetLowering()
402 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
440 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); in AArch64TargetLowering()
645 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); in AArch64TargetLowering()
1471 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in emitComparison()
1472 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in emitComparison()
1577 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitConditionalComparison()
1578 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitConditionalComparison()
2254 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp163 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
303 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); in AArch64TargetLowering()
309 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
369 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); in AArch64TargetLowering()
547 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); in AArch64TargetLowering()
1212 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in emitComparison()
1213 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in emitComparison()
1304 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitConditionalComparison()
1305 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitConditionalComparison()
1930 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp3599 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
3607 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
3619 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
3625 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
3631 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
3637 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
3649 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in LowerFP_TO_INT()
5239 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); in PerformDAGCombine()
5269 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); in PerformDAGCombine()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1182 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, in getCastInstrCost()
1183 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
1273 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, in getCastInstrCost()
1351 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, in getCastInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp266 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand); in SITargetLowering()
537 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand); in SITargetLowering()
2562 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
4021 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) : in getFPExtOrFPTrunc()
5825 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0); in LowerFDIV16()
5826 SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in LowerFDIV16()
6833 case ISD::FP_EXTEND: in isCanonicalized()
7580 Op1.getOpcode() != ISD::FP_EXTEND || in performFMACombine()
7581 Op2.getOpcode() != ISD::FP_EXTEND) in performFMACombine()
7605 if (FMAOp1.getOpcode() != ISD::FP_EXTEND || in performFMACombine()
[all …]

123