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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dhello-reloc.s5 …apple-darwin8 %s -o - | llvm-readobj -r --expand-relocs | FileCheck -check-prefix=DARWIN-G4-DUMP %s
60 ; DARWIN-G4-DUMP:Format: Mach-O 32-bit ppc
61 ; DARWIN-G4-DUMP:Arch: powerpc
62 ; DARWIN-G4-DUMP:AddressSize: 32bit
63 ; DARWIN-G4-DUMP:Relocations [
64 ; DARWIN-G4-DUMP: Section __text {
65 ; DARWIN-G4-DUMP: Relocation {
66 ; DARWIN-G4-DUMP: Offset: 0x34
67 ; DARWIN-G4-DUMP: PCRel: 1
68 ; DARWIN-G4-DUMP: Length: 2
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dhello-reloc.s5 …apple-darwin8 %s -o - | llvm-readobj -r --expand-relocs | FileCheck -check-prefix=DARWIN-G4-DUMP %s
60 ; DARWIN-G4-DUMP:Format: Mach-O 32-bit ppc
61 ; DARWIN-G4-DUMP:Arch: powerpc
62 ; DARWIN-G4-DUMP:AddressSize: 32bit
63 ; DARWIN-G4-DUMP:Relocations [
64 ; DARWIN-G4-DUMP: Section __text {
65 ; DARWIN-G4-DUMP: Relocation {
66 ; DARWIN-G4-DUMP: Offset: 0x34
67 ; DARWIN-G4-DUMP: PCRel: 1
68 ; DARWIN-G4-DUMP: Length: 2
[all …]
/external/mesa3d/src/mesa/program/
Dprog_noise.c482 #define G4 0.138196601f /* G4 = (5.0-Math.sqrt(5.0))/20.0 */ in _mesa_noise4() macro
497 float t = (i + j + k + l) * G4; /* Factor for 4D unskewing */ in _mesa_noise4()
558 x1 = x0 - i1 + G4; /* Offsets for second corner in (x,y,z,w) coords */ in _mesa_noise4()
559 y1 = y0 - j1 + G4; in _mesa_noise4()
560 z1 = z0 - k1 + G4; in _mesa_noise4()
561 w1 = w0 - l1 + G4; in _mesa_noise4()
562 x2 = x0 - i2 + 2.0f * G4; /* Offsets for third corner in (x,y,z,w) coords */ in _mesa_noise4()
563 y2 = y0 - j2 + 2.0f * G4; in _mesa_noise4()
564 z2 = z0 - k2 + 2.0f * G4; in _mesa_noise4()
565 w2 = w0 - l2 + 2.0f * G4; in _mesa_noise4()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/XCore/
Dglobals.ll28 ; CHECK: ldaw r0, dp[G4]
29 ret i32** @G4
74 @G4 = global i32* @G1
76 ; CHECK: G4:
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/GlobalOpt/
Dglobal-demotion.ll6 @G4 = internal global i32 5
46 ; CHECK-NOT: %G4
47 store i32 4, i32* @G4
48 %x = bitcast i32* @G4 to i64*
/external/llvm/test/Transforms/GlobalOpt/
Dglobal-demotion.ll6 @G4 = internal global i32 5
46 ; CHECK-NOT: %G4
47 store i32 4, i32* @G4
48 %x = bitcast i32* @G4 to i64*
/external/llvm/test/CodeGen/XCore/
Dglobals.ll35 ; CHECK: ldaw r0, dp[G4]
36 ret i32** @G4
99 @G4 = global i32* @G1
101 ; CHECK: G4:
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/XCore/
Dglobals.ll35 ; CHECK: ldaw r0, dp[G4]
36 ret i32** @G4
99 @G4 = global i32* @G1
101 ; CHECK: G4:
/external/epid-sdk/ext/ipp/sources/ippcp/
Dpcphashmd5px.c100 #define G4 20 macro
174 MD5_STEP(G, b,c,d,a, data[ 0], MD5_cnt_loc[19], G4); in UpdateMD5()
178 MD5_STEP(G, b,c,d,a, data[ 4], MD5_cnt_loc[23], G4); in UpdateMD5()
182 MD5_STEP(G, b,c,d,a, data[ 8], MD5_cnt_loc[27], G4); in UpdateMD5()
186 MD5_STEP(G, b,c,d,a, data[12], MD5_cnt_loc[31], G4); in UpdateMD5()
/external/ltp/testcases/kernel/syscalls/ptrace/
Dsimple_tracer.c83 #define G4 u_regs[3] in decode_regs()
98 decode(G4); in decode_regs()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
Ddag-combine-ossfuzz-crash.ll20 %G4 = getelementptr i66, i66* %A4, i1 true
21 %L6 = load i66, i66* %G4
/external/webp/src/dsp/
Dcommon_sse41.h42 __m128i G0, G1, G2, G3, G4, G5; in VP8PlanarTo24b_SSE41() local
86 const __m128i RG4 = _mm_or_si128(R4, G4); in VP8PlanarTo24b_SSE41()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCScheduleG4.td1 //===- PPCScheduleG4.td - PPC G4 Scheduling Definitions ----*- tablegen -*-===//
10 // This file defines the itinerary class data for the G4 (7400) processor.
DPPCScheduleG4Plus.td1 //===- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. -----*- tablegen -*-===//
10 // This file defines the itinerary class data for the G4+ (7450) processor.
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcRegisterInfo.td56 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
148 G2, G3, G4, // FIXME: OK for use only in
/external/error_prone/error_prone/
Derror_prone_type_annotations-2.3.2.jar.asc11 65G4+Z+c7vup2hkokzPBIy0AxVcfLLVAsA2CTZGrf62eq3fpBSZMwo+P2yBXb0fB
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCScheduleG4.td1 //===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===//
10 // This file defines the itinerary class data for the G4 (7400) processor.
DPPCScheduleG4Plus.td1 //===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
10 // This file defines the itinerary class data for the G4+ (7450) processor.
/external/llvm/lib/Target/PowerPC/
DPPCScheduleG4.td1 //===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===//
10 // This file defines the itinerary class data for the G4 (7400) processor.
DPPCScheduleG4Plus.td1 //===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
10 // This file defines the itinerary class data for the G4+ (7450) processor.
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dglobal-sections.ll43 ; _Complex long long const G4 = 34;
44 @G4 = unnamed_addr constant {i64,i64} { i64 34, i64 0 }
/external/clang/test/SemaOpenCL/
Dstorageclass-cl20.cl6 local int G4 = 0; // expected-error{{program scope variable must reside in global or c…
/external/libffi/m4/
Dax_gcc_archflag.m4184 *740[[0-9]]*) ax_gcc_arch="$cputype 7400 G4" ;;
185 *74[[4-5]][[0-9]]*) ax_gcc_arch="$cputype 7450 G4" ;;
186 *74[[0-9]][[0-9]]*) ax_gcc_arch="$cputype G4" ;;
/external/python/cpython2/Modules/_ctypes/libffi/m4/
Dax_gcc_archflag.m4184 *740[[0-9]]*) ax_gcc_arch="$cputype 7400 G4" ;;
185 *74[[4-5]][[0-9]]*) ax_gcc_arch="$cputype 7450 G4" ;;
186 *74[[0-9]][[0-9]]*) ax_gcc_arch="$cputype G4" ;;
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dand-or-icmps.ll226 %G4 = getelementptr i16, i16* %A8, i16 %B11
227 %L2 = load i16, i16* %G4
228 %L = load i16, i16* %G4

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