| /external/swiftshader/third_party/LLVM/lib/Transforms/Utils/ |
| D | AddrModeMatcher.cpp | 269 if (AddrMode.HasBaseReg) { in MatchOperationAddr()
274 AddrMode.HasBaseReg = true; in MatchOperationAddr()
285 if (AddrMode.HasBaseReg) in MatchOperationAddr()
287 AddrMode.HasBaseReg = true; in MatchOperationAddr()
354 if (!AddrMode.HasBaseReg) { in MatchAddr()
355 AddrMode.HasBaseReg = true; in MatchAddr()
360 AddrMode.HasBaseReg = false; in MatchAddr()
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| /external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/ |
| D | AddrModeMatcher.h | 46 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale);
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| /external/llvm/include/llvm/Analysis/ |
| D | TargetTransformInfoImpl.h | 205 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
221 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
223 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
446 bool HasBaseReg = (BaseGV == nullptr); in getGEPCost() local
483 BaseOffset, HasBaseReg, Scale, AS)) { in getGEPCost()
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| D | TargetTransformInfo.h | 330 bool HasBaseReg, int64_t Scale,
351 bool HasBaseReg, int64_t Scale,
652 int64_t BaseOffset, bool HasBaseReg,
660 int64_t BaseOffset, bool HasBaseReg,
800 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
802 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
818 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
820 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
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| /external/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 236 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference() local
237 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in printLeaMemReference()
239 HasBaseReg = false; in printLeaMemReference()
242 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
266 if (HasBaseReg) in printLeaMemReference()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 264 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference() local
265 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in printLeaMemReference()
267 HasBaseReg = false; in printLeaMemReference()
270 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
294 if (HasBaseReg) in printLeaMemReference()
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| /external/llvm/lib/Analysis/ |
| D | TargetTransformInfo.cpp | 119 bool HasBaseReg, in isLegalAddressingMode() argument
122 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
144 bool HasBaseReg, in getScalingFactorCost() argument
147 int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 287 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference() local
288 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in printLeaMemReference()
290 HasBaseReg = false; in printLeaMemReference()
293 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
313 if (HasBaseReg) in printLeaMemReference()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 253 bool HasBaseReg; member
280 : BaseGV(nullptr), BaseOffset(0), HasBaseReg(false), Scale(0), in Formula()
369 HasBaseReg = true; in initialMatch()
375 HasBaseReg = true; in initialMatch()
480 if (HasBaseReg && BaseRegs.empty()) { in print()
483 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1359 bool HasBaseReg, int64_t Scale) { in isAMCompletelyFolded() argument
1363 HasBaseReg, Scale, AccessTy.AddrSpace); in isAMCompletelyFolded()
1372 if (Scale != 0 && HasBaseReg && BaseOffset != 0) in isAMCompletelyFolded()
1412 bool HasBaseReg, int64_t Scale) { in isAMCompletelyFolded() argument
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 318 bool HasBaseReg = false; member
438 HasBaseReg = true; in initialMatch()
444 HasBaseReg = true; in initialMatch()
588 if (HasBaseReg && BaseRegs.empty()) { in print()
591 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1203 bool HasBaseReg, int64_t Scale,
1352 Offset, F.HasBaseReg, F.Scale, Fixup.UserInst)) in RateFormula()
1603 bool HasBaseReg, int64_t Scale, in isAMCompletelyFolded() argument
1608 HasBaseReg, Scale, AccessTy.AddrSpace, Fixup); in isAMCompletelyFolded()
1617 if (Scale != 0 && HasBaseReg && BaseOffset != 0) in isAMCompletelyFolded()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Analysis/ |
| D | TargetTransformInfoImpl.h | 236 bool HasBaseReg, int64_t Scale,
269 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
271 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
709 bool HasBaseReg = (BaseGV == nullptr); in getGEPCost() local
757 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, AS)) in getGEPCost()
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| D | TargetTransformInfo.h | 473 bool HasBaseReg, int64_t Scale,
525 bool HasBaseReg, int64_t Scale,
1034 int64_t BaseOffset, bool HasBaseReg,
1050 int64_t BaseOffset, bool HasBaseReg,
1256 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
1259 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
1294 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
1296 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
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| /external/llvm/include/llvm/CodeGen/ |
| D | BasicTTIImpl.h | 127 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
132 AM.HasBaseReg = HasBaseReg; in isLegalAddressingMode()
138 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
142 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
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| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 318 AM.HasBaseReg = true; in InitialMatch()
324 AM.HasBaseReg = true; in InitialMatch()
386 if (AM.HasBaseReg && BaseRegs.empty()) { in print()
389 } else if (!AM.HasBaseReg && !BaseRegs.empty()) { in print()
1197 if (AM.Scale != 0 && AM.HasBaseReg && AM.BaseOffs != 0) in isLegalUse()
1249 bool HasBaseReg, in isAlwaysFoldable() argument
1260 AM.HasBaseReg = HasBaseReg; in isAlwaysFoldable()
1265 if (!AM.HasBaseReg && AM.Scale == 1) { in isAlwaysFoldable()
1267 AM.HasBaseReg = true; in isAlwaysFoldable()
1275 bool HasBaseReg, in isAlwaysFoldable() argument
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | BasicTTIImpl.h | 166 bool HasBaseReg, int64_t Scale,
171 AM.HasBaseReg = HasBaseReg;
193 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
197 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | TargetTransformInfo.cpp | 146 bool HasBaseReg, in isLegalAddressingMode() argument
150 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
197 bool HasBaseReg, in getScalingFactorCost() argument
200 int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
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| /external/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 2093 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale); in operator ==()
3285 if (AddrMode.HasBaseReg) { in matchOperationAddr()
3290 AddrMode.HasBaseReg = true; in matchOperationAddr()
3301 if (AddrMode.HasBaseReg) in matchOperationAddr()
3303 AddrMode.HasBaseReg = true; in matchOperationAddr()
3436 if (!AddrMode.HasBaseReg) { in matchAddr()
3437 AddrMode.HasBaseReg = true; in matchAddr()
3442 AddrMode.HasBaseReg = false; in matchAddr()
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| D | TargetLoweringBase.cpp | 1795 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1800 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPerfHintAnalysis.cpp | 251 AM.HasBaseReg = !AM.BaseGV; in visit()
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetLowering.h | 1529 bool HasBaseReg; member
1531 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 2802 !NewAddrMode.HasBaseReg); in addNewAddrMode()
3907 if (AddrMode.HasBaseReg) { in matchOperationAddr()
3912 AddrMode.HasBaseReg = true; in matchOperationAddr()
3923 if (AddrMode.HasBaseReg) in matchOperationAddr()
3925 AddrMode.HasBaseReg = true; in matchOperationAddr()
4058 if (!AddrMode.HasBaseReg) { in matchAddr()
4059 AddrMode.HasBaseReg = true; in matchAddr()
4064 AddrMode.HasBaseReg = false; in matchAddr()
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| D | TargetLoweringBase.cpp | 1601 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1606 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1593 bool HasBaseReg; member
1595 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 742 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { in isLegalAddressingMode()
754 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) { in isLegalAddressingMode()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 320 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
389 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
410 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
|