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Searched refs:IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/board/kosagi/novena/
Dvideo.c424 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK, in setup_display_clock()
/external/u-boot/board/advantech/dms-ba16/
Ddms-ba16.c429 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | in setup_display()
/external/u-boot/board/ge/bx50v3/
Dbx50v3.c492 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | in setup_display_b850v3()
/external/u-boot/board/freescale/mx6sabresd/
Dmx6sabresd.c536 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK in setup_display()
/external/u-boot/board/congatec/cgtqmx6eval/
Dcgtqmx6eval.c667 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | in setup_display()
/external/u-boot/arch/arm/include/asm/arch-mx6/
Dimx-regs.h563 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) macro