| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrDesc.h | 144 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr variable
234 return ImplicitDefs; in getImplicitDefs()
240 if (ImplicitDefs == 0) return 0; in getNumImplicitDefs()
242 for (; ImplicitDefs[i]; ++i) /*empty*/; in getNumImplicitDefs()
258 if (const unsigned *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 148 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr variable
497 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
501 if (!ImplicitDefs) in getNumImplicitDefs()
504 for (; ImplicitDefs[i]; ++i) /*empty*/ in getNumImplicitDefs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 172 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr variable
539 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
543 if (!ImplicitDefs) in getNumImplicitDefs()
546 for (; ImplicitDefs[i]; ++i) /*empty*/ in getNumImplicitDefs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineCSE.cpp | 476 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlock() local
570 ImplicitDefs.push_back(OldReg); in ProcessBlock()
632 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
639 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
667 ImplicitDefs.clear(); in ProcessBlock()
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| /external/llvm/lib/CodeGen/ |
| D | MachineCSE.cpp | 455 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlock() local
550 ImplicitDefs.push_back(OldReg); in ProcessBlock()
611 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
618 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
646 ImplicitDefs.clear(); in ProcessBlock()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | InstrDocsEmitter.cpp | 191 if (!II->ImplicitDefs.empty()) { in EmitInstrDocs()
194 for (Record *Def : II->ImplicitDefs) { in EmitInstrDocs()
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| D | CodeGenInstruction.cpp | 347 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
380 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
383 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
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| D | CodeGenInstruction.h | 221 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
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| D | DAGISelMatcherGen.cpp | 813 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
955 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1124 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_r()
1146 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rr()
1170 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rrr()
1191 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ri()
1214 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rii()
1235 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rf()
1259 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rri()
1275 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_i()
1292 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ii()
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| D | ScheduleDAGFast.cpp | 426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
509 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
511 for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg) { in DelayForLiveRegsBottomUp()
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| /external/capstone/ |
| D | MCInstrDesc.h | 132 char ImplicitDefs; // Registers implicitly defined by this instr member
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| D | MCInstrDesc.cpp | 56 if (const MCPhysReg *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
|
| /external/llvm/lib/MC/ |
| D | MCInstrDesc.cpp | 56 if (const MCPhysReg *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 322 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
340 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
343 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
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| D | CodeGenInstruction.h | 216 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
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| D | DAGISelMatcherGen.cpp | 782 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
907 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 342 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
371 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
374 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
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| D | CodeGenInstruction.h | 221 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
|
| D | DAGISelMatcherGen.cpp | 849 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
972 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1830 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
1855 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
1883 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
1905 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
1930 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
1949 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_f()
1975 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
1991 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
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| D | ScheduleDAGFast.cpp | 441 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
520 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 301 .addReg(II.ImplicitDefs[0])); in FastEmitInst_r()
323 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rr()
348 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rrr()
370 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ri()
392 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rf()
417 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rri()
436 .addReg(II.ImplicitDefs[0])); in FastEmitInst_i()
456 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ii()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 2023 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
2048 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
2076 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
2098 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
2123 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
2142 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_f()
2168 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
2184 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
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| D | ScheduleDAGFast.cpp | 435 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
513 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
|