| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 47 SDValue IndexReg; member
52 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) { in SystemZRRIAddressMode()
69 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump(); in dump()
232 if (AM.IndexReg.getNode() || AM.isRI) { in MatchAddress()
249 AM.IndexReg = Neg; in MatchAddress()
281 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) { in MatchAddress()
283 AM.IndexReg = N.getNode()->getOperand(1); in MatchAddress()
322 if (AM.IndexReg.getNode() == 0 && !AM.isRI) { in MatchAddressBase()
323 AM.IndexReg = N; in MatchAddressBase()
350 Index = AM.IndexReg; in getAddressOperands()
[all …]
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| D | SystemZInstrBuilder.h | 45 unsigned IndexReg; member
49 SystemZAddressMode() : BaseType(RegBase), IndexReg(0), Disp(0) { in SystemZAddressMode()
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg); in addFullAddress()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 337 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon3ca5b30f0111::X86AsmParser::IntelExprStateMachine
348 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), in IntelExprStateMachine()
356 unsigned getIndexReg() { return IndexReg; } in getIndexReg()
459 if (IndexReg) { in onPlus()
463 IndexReg = TmpReg; in onPlus()
512 if (IndexReg) { in onMinus()
516 IndexReg = TmpReg; in onMinus()
568 if (IndexReg) { in onRegister()
573 IndexReg = Reg; in onRegister()
645 if (IndexReg) { in onInteger()
[all …]
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| D | X86Operand.h | 62 unsigned IndexReg; member
136 if (Mem.IndexReg) in print()
138 << X86IntelInstPrinter::getRegisterName(Mem.IndexReg); in print()
188 return Mem.IndexReg; in getMemIndexReg()
311 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
574 Res->Mem.IndexReg = 0;
588 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
593 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
602 Res->Mem.IndexReg = IndexReg;
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 49 unsigned IndexReg; member
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
104 AM.IndexReg = Op.getImm(); in getAddressFromInstr()
162 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
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| D | X86AsmPrinter.cpp | 232 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printLeaMemReference() local
242 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
262 assert(IndexReg.getReg() != X86::ESP && in printLeaMemReference()
269 if (IndexReg.getReg()) { in printLeaMemReference()
298 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printIntelMemReference() local
316 if (IndexReg.getReg()) { in printIntelMemReference()
329 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printIntelMemReference()
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| D | X86ISelDAGToDAG.cpp | 62 SDValue IndexReg; member
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
114 if (IndexReg.getNode()) in dump()
115 IndexReg.getNode()->dump(); in dump()
254 Index = AM.IndexReg; in getAddressOperands()
847 AM.Base_Reg = AM.IndexReg; in matchAddress()
859 AM.IndexReg.getNode() == nullptr && in matchAddress()
890 !AM.IndexReg.getNode()) { in matchAdd()
893 AM.IndexReg = N.getOperand(1); in matchAdd()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 111 const MCOperand &IndexReg = MI->getOperand(Op+2); in printMemReference() local
123 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
130 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
135 if (IndexReg.getReg()) { in printMemReference()
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| D | X86IntelInstPrinter.cpp | 99 const MCOperand &IndexReg = MI->getOperand(Op+2); in printMemReference() local
117 if (IndexReg.getReg()) { in printMemReference()
132 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 55 unsigned IndexReg; member
61 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
78 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
109 AM.IndexReg = Op2.getReg(); in getAddressFromInstr()
184 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
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| D | X86AsmPrinter.cpp | 260 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printLeaMemReference() local
270 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
290 assert(IndexReg.getReg() != X86::ESP && in printLeaMemReference()
297 if (IndexReg.getReg()) { in printLeaMemReference()
326 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printIntelMemReference() local
344 if (IndexReg.getReg()) { in printIntelMemReference()
357 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printIntelMemReference()
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| D | X86ISelDAGToDAG.cpp | 62 SDValue IndexReg; member
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
115 if (IndexReg.getNode()) in dump()
116 IndexReg.getNode()->dump(DAG); in dump()
261 Index = AM.IndexReg; in getAddressOperands()
1059 AM.Base_Reg = AM.IndexReg; in matchAddress()
1071 AM.IndexReg.getNode() == nullptr && in matchAddress()
1102 !AM.IndexReg.getNode()) { in matchAdd()
1105 AM.IndexReg = N.getOperand(1); in matchAdd()
[all …]
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anonf33d2cb70111::X86AsmParser::IntelExprStateMachine
274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
279 unsigned getIndexReg() { return IndexReg; } in getIndexReg()
387 assert (!IndexReg && "BaseReg/IndexReg already set!"); in onPlus()
388 IndexReg = TmpReg; in onPlus()
424 assert (!IndexReg && "BaseReg/IndexReg already set!"); in onMinus()
425 IndexReg = TmpReg; in onMinus()
461 assert (!IndexReg && "IndexReg already set!"); in onRegister()
463 IndexReg = Reg; in onRegister()
511 assert (!IndexReg && "IndexReg already set!"); in onInteger()
[all …]
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| D | X86Operand.h | 56 unsigned IndexReg; member
121 return Mem.IndexReg; in getMemIndexReg()
238 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
504 Res->Mem.IndexReg = 0;
517 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
522 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
531 Res->Mem.IndexReg = IndexReg;
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is16BitMemOperand() local
69 (IndexReg.getReg() != 0 && in Is16BitMemOperand()
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) in Is16BitMemOperand()
207 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand() local
211 (IndexReg.getReg() != 0 && in Is32BitMemOperand()
212 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in Is32BitMemOperand()
215 assert(IndexReg.getReg() == 0 && "Invalid eip-based address."); in Is32BitMemOperand()
226 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is64BitMemOperand() local
230 (IndexReg.getReg() != 0 && in Is64BitMemOperand()
231 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) in Is64BitMemOperand()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrBuilder.h | 50 unsigned IndexReg; member
56 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) { in X86AddressMode()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
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| D | X86ISelDAGToDAG.cpp | 64 SDValue IndexReg; member
76 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
86 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0; in hasBaseOrIndexReg()
114 if (IndexReg.getNode() != 0) in dump()
115 IndexReg.getNode()->dump(); in dump()
237 Index = AM.IndexReg; in getAddressOperands()
708 AM.Base_Reg = AM.IndexReg; in MatchAddress()
720 AM.IndexReg.getNode() == 0 && in MatchAddress()
785 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) in MatchAddressRecursively()
803 AM.IndexReg = ShVal.getNode()->getOperand(0); in MatchAddressRecursively()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 69 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is16BitMemOperand() local
77 (IndexReg.getReg() != 0 && in Is16BitMemOperand()
78 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) in Is16BitMemOperand()
211 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand() local
215 (IndexReg.getReg() != 0 && in Is32BitMemOperand()
216 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in Is32BitMemOperand()
219 assert(IndexReg.getReg() == 0 && "Invalid eip-based address."); in Is32BitMemOperand()
222 if (IndexReg.getReg() == X86::EIZ) in Is32BitMemOperand()
232 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is64BitMemOperand() local
236 (IndexReg.getReg() != 0 && in Is64BitMemOperand()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 114 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
124 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
131 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
136 if (IndexReg.getReg()) { in printMemReference()
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| D | X86IntelInstPrinter.cpp | 76 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
90 if (IndexReg.getReg()) { in printMemReference()
104 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 136 unsigned IndexReg; member
185 return Mem.IndexReg; in getMemIndexReg()
345 Res->Mem.IndexReg = 0; in CreateMem()
352 unsigned BaseReg, unsigned IndexReg, in CreateMem()
356 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!"); in CreateMem()
365 Res->Mem.IndexReg = IndexReg; in CreateMem()
380 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0); in isSrcOp()
389 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0; in isDstOp()
581 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
603 if (ParseRegister(IndexReg, L, L)) return 0; in ParseMemOperand()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 163 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand() local
167 (IndexReg.getReg() != 0 && in Is32BitMemOperand()
168 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in Is32BitMemOperand()
249 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in EmitMemModRMByte() local
255 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); in EmitMemModRMByte()
286 IndexReg.getReg() == 0 && in EmitMemModRMByte()
325 assert(IndexReg.getReg() != X86::ESP && in EmitMemModRMByte()
326 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); in EmitMemModRMByte()
362 if (IndexReg.getReg()) in EmitMemModRMByte()
363 IndexRegNo = GetX86RegNum(IndexReg); in EmitMemModRMByte()
[all …]
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 198 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
212 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
219 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
224 if (IndexReg.getReg()) { in printMemReference()
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| D | X86IntelInstPrinter.cpp | 161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
179 if (IndexReg.getReg()) { in printMemReference()
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/MCParser/ |
| D | MCTargetAsmParser.h | 66 StringRef IndexReg; member
70 BaseReg(StringRef()), IndexReg(StringRef()), in NeedBracs()
81 IndexReg = reg; in IntelExpr()
95 return IndexReg.size(); in hasIndexReg()
|