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Searched refs:KS2_DDRPHY_ZQ0CR1_OFFSET (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-keystone/include/mach/
Dhardware.h49 #define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184 macro
/external/u-boot/arch/arm/mach-keystone/
Dddr3.c58 __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET); in ddr3_init_ddrphy()