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Searched refs:LRE (Results 1 – 25 of 43) sorted by relevance

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/external/icu/icu4c/source/test/cintltst/
Dcbididat.c163 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
164 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
165 AN, RLO, NSM, LRE, PDF, RLE, ES, EN, ON /* 9 entries */
184 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
185 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
186 LRE, BN, CS, RLO, S, PDF, EN, LRO, AN, ES /* 10 entries */
206 WS, LRE, WS, R, R, R, WS, PDF, WS, L, L, L, WS, PDF, WS, AL, AL, AL, WS, PDF, /* 20 entries */
285 ON, L, RLO, CS, R, WS, AN, AN, PDF, LRE, R, L, LRO, WS, BN, ON, S, LRE, LRO, B
Dcbiditst.h45 #define LRE U_LEFT_TO_RIGHT_EMBEDDING macro
/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/bidi/
DTestData.java37 protected static final int LRE = UCharacterDirection.LEFT_TO_RIGHT_EMBEDDING; field in TestData
65 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
66 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
67 AN, RLO, NSM, LRE, PDF, RLE, ES, EN, ON /* 9 entries */
70 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
71 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
72 LRE, BN, CS, RLO, S, PDF, EN, LRO, AN, ES /* 10 entries */
75 L, WS, LRE, WS, R, R, R, WS, PDF, WS, L, L, L, WS, PDF, WS, AL, AL,
98 { ON, L, RLO, CS, R, WS, AN, AN, PDF, LRE, R, L, LRO, WS, BN, ON, S,
99 LRE, LRO, B }, // 15
[all …]
DTestClassOverride.java34 private static final int LRE = TestData.LRE; field in TestClassOverride
57 R, R, R, LRE, DEF, RLE, PDF, S, //58-5F
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/bidi/
DTestData.java34 protected static final int LRE = UCharacterDirection.LEFT_TO_RIGHT_EMBEDDING; field in TestData
62 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
63 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
64 AN, RLO, NSM, LRE, PDF, RLE, ES, EN, ON /* 9 entries */
67 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
68 LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, LRE, /* 15 entries */
69 LRE, BN, CS, RLO, S, PDF, EN, LRO, AN, ES /* 10 entries */
72 L, WS, LRE, WS, R, R, R, WS, PDF, WS, L, L, L, WS, PDF, WS, AL, AL,
95 { ON, L, RLO, CS, R, WS, AN, AN, PDF, LRE, R, L, LRO, WS, BN, ON, S,
96 LRE, LRO, B }, // 15
[all …]
DTestClassOverride.java31 private static final int LRE = TestData.LRE; field in TestClassOverride
54 R, R, R, LRE, DEF, RLE, PDF, S, //58-5F
/external/icu/icu4c/source/test/testdata/
DBidiTest.txt74 # L LRE R R; 7
75 # L LRE R AL; 7
95 # input lines have the same result (0), since the LRE (item 1) is omitted on the second line.
98 # L LRE; 7
103 LRE; 7
160 LRE LRE; 7
161 LRE LRO; 7
162 LRE RLE; 7
163 LRE RLO; 7
164 LRE PDF; 7
[all …]
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/
DBidiTest.txt74 # L LRE R R; 7
75 # L LRE R AL; 7
95 # input lines have the same result (0), since the LRE (item 1) is omitted on the second line.
98 # L LRE; 7
103 LRE; 7
160 LRE LRE; 7
161 LRE LRO; 7
162 LRE RLE; 7
163 LRE RLO; 7
164 LRE PDF; 7
[all …]
/external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/
DBidiTest.txt74 # L LRE R R; 7
75 # L LRE R AL; 7
95 # input lines have the same result (0), since the LRE (item 1) is omitted on the second line.
98 # L LRE; 7
103 LRE; 7
160 LRE LRE; 7
161 LRE LRO; 7
162 LRE RLE; 7
163 LRE RLO; 7
164 LRE PDF; 7
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DSpiller.cpp183 void spill(LiveRangeEdit &LRE) { in spill() argument
185 trivialSpillEverywhere(&LRE.getParent(), *LRE.getNewVRegs()); in spill()
211 void spill(LiveRangeEdit &LRE) { in spill() argument
213 lis->addIntervalsForSpills(LRE.getParent(), LRE.getUselessVRegs(), in spill()
215 LRE.getNewVRegs()->insert(LRE.getNewVRegs()->end(), in spill()
219 int SS = vrm->getStackSlot(LRE.getReg()); in spill()
222 const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg()); in spill()
226 SI.MergeRangesInAsValue(LRE.getParent(), SI.getValNumInfo(0)); in spill()
DRegAllocFast.cpp162 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
163 void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
470 void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) { in assignVirtToPhysReg() argument
471 DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to " in assignVirtToPhysReg()
473 PhysRegState[PhysReg] = LRE.first; in assignVirtToPhysReg()
474 assert(!LRE.second.PhysReg && "Already assigned a physreg"); in assignVirtToPhysReg()
475 LRE.second.PhysReg = PhysReg; in assignVirtToPhysReg()
479 void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) { in allocVirtReg() argument
480 const unsigned VirtReg = LRE.first; in allocVirtReg()
499 return assignVirtToPhysReg(LRE, Hint); in allocVirtReg()
[all …]
DRegAllocBasic.cpp394 LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills); in spillReg() local
395 spiller().spill(LRE); in spillReg()
527 LiveRangeEdit LRE(VirtReg, SplitVRegs); in selectOrSplit() local
528 spiller().spill(LRE); in selectOrSplit()
DSpiller.h29 virtual void spill(LiveRangeEdit &LRE) = 0;
DRegAllocLinearScan.cpp1233 LiveRangeEdit LRE(*cur, added); in assignRegOrStackSlotAtInterval() local
1234 spiller_->spill(LRE); in assignRegOrStackSlotAtInterval()
1310 LiveRangeEdit LRE(*sli, added, 0, &spillIs); in assignRegOrStackSlotAtInterval() local
1311 spiller_->spill(LRE); in assignRegOrStackSlotAtInterval()
/external/syzkaller/vendor/golang.org/x/text/unicode/bidi/
Dtrieval.go29 LRE // LeftToRightEmbedding const
43 0x202A: LRE, // LeftToRightEmbedding,
Dgen_trieval.go33 LRE // LeftToRightEmbedding const
47 0x202A: LRE, // LeftToRightEmbedding,
Dcore.go302 case RLE, LRE, RLO, LRO, RLI, LRI, FSI:
810 if t.in(LRE, RLE, LRO, RLO, PDF, BN) {
981 case LRE, RLE, LRO, RLO, PDF, LRI, RLI, FSI, PDI, BN, WS:
990 case LRE, RLE, LRO, RLO, PDF, BN:
Dprop.go51 0xA: LRE, // U+202A LeftToRightEmbedding,
/external/llvm/lib/CodeGen/
DRegAllocBasic.cpp202 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats); in spillInterferences() local
203 spiller().spill(LRE); in spillInterferences()
261 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats); in selectOrSplit() local
262 spiller().spill(LRE); in selectOrSplit()
DSpiller.h31 virtual void spill(LiveRangeEdit &LRE) = 0;
DRegAllocPBQP.cpp641 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM, in spillVReg() local
643 VRegSpiller.spill(LRE); in spillVReg()
648 << LRE.getParent().weight << ", New vregs: "); in spillVReg()
652 for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end(); in spillVReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegAllocBasic.cpp239 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); in spillInterferences() local
240 spiller().spill(LRE); in spillInterferences()
298 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); in selectOrSplit() local
299 spiller().spill(LRE); in selectOrSplit()
DSpiller.h31 virtual void spill(LiveRangeEdit &LRE) = 0;
DRegAllocPBQP.cpp682 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM, in spillVReg() local
684 VRegSpiller.spill(LRE); in spillVReg()
689 << LRE.getParent().weight << ", New vregs: "); in spillVReg()
693 for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end(); in spillVReg()
/external/icu/icu4c/source/common/
Dubidiimp.h48 LRE=U_LEFT_TO_RIGHT_EMBEDDING, /* 11 */ enumerator
77 …FLAG(EN)|DIRPROP_FLAG(ENL)|DIRPROP_FLAG(ENR)|DIRPROP_FLAG(AN)|DIRPROP_FLAG(LRE)|DIRPROP_FLAG(LRO)|…
83 #define MASK_EXPLICIT (DIRPROP_FLAG(LRE)|DIRPROP_FLAG(LRO)|DIRPROP_FLAG(RLE)|DIRPROP_FLAG(RLO)|DIRP…

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