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Searched refs:MAX_PHASE_RL_UL_2TO1 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_hw_training.h184 #define MAX_PHASE_RL_UL_2TO1 3 macro
Dddr3_read_leveling.c588 if (phase < MAX_PHASE_RL_UL_2TO1) in ddr3_read_leveling_single_cs_rl_mode()
1005 if (phase < MAX_PHASE_RL_UL_2TO1) in ddr3_read_leveling_single_cs_window_mode()