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Searched refs:MAX_SETS (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_descriptor_set.h29 #define MAX_SETS 32 macro
82 } set[MAX_SETS];
Dradv_cmd_buffer.c502 uint32_t data[MAX_SETS * 2] = {}; in radv_save_descriptors()
508 cmd_buffer->cs, 4 + MAX_SETS * 2); in radv_save_descriptors()
517 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data); in radv_save_descriptors()
1721 uint32_t size = MAX_SETS * 2 * 4; in radv_flush_indirect_descriptor_sets()
1729 for (unsigned i = 0; i < MAX_SETS; i++) { in radv_flush_indirect_descriptor_sets()
1788 MAX_SETS * MESA_SHADER_STAGES * 4); in radv_flush_descriptors()
Dradv_debug.c322 for (i = 0; i < MAX_SETS; i++) { in radv_dump_descriptors()
Dradv_private.h975 struct radv_descriptor_set *descriptors[MAX_SETS];
Dradv_device.c662 .maxBoundDescriptorSets = MAX_SETS, in radv_GetPhysicalDeviceProperties()
/external/mesa3d/src/amd/common/
Dac_nir_to_llvm.h132 #define AC_UD_MAX_SETS MAX_SETS
/external/mesa3d/src/intel/vulkan/
Danv_private.h98 #define MAX_SETS 8 macro
1403 } set[MAX_SETS];
1679 struct anv_descriptor_set *descriptors[MAX_SETS];
1682 struct anv_push_descriptor_set *push_descriptors[MAX_SETS];
Danv_cmd_buffer.c565 assert(firstSet + descriptorSetCount < MAX_SETS); in anv_CmdBindDescriptorSets()
914 assert(_set < MAX_SETS); in anv_CmdPushDescriptorSetKHR()
Danv_nir_apply_pipeline_layout.c40 } set[MAX_SETS];
DgenX_cmd_buffer.c1522 assert(binding->set < MAX_SETS); in anv_descriptor_for_binding()
1535 assert(binding->set < MAX_SETS); in dynamic_offset_for_binding()
Danv_device.c832 .maxBoundDescriptorSets = MAX_SETS, in anv_GetPhysicalDeviceProperties()