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Searched refs:MII_BMCR (Results 1 – 25 of 42) sorted by relevance

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/external/u-boot/drivers/qe/
Duec_phy.c259 ctrl = uec_phy_read(mii_info, MII_BMCR); in genmii_setup_forced()
289 uec_phy_write(mii_info, MII_BMCR, ctrl); in genmii_setup_forced()
297 ctl = uec_phy_read(mii_info, MII_BMCR); in genmii_restart_aneg()
299 uec_phy_write(mii_info, MII_BMCR, ctl); in genmii_restart_aneg()
334 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); in marvell_config_aneg()
511 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); in uec_marvell_init()
583 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) | in dm9161_init()
586 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) & in dm9161_init()
899 status = uec_phy_read(mii_info, MII_BMCR); in marvell_phy_interface_mode()
900 uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE); in marvell_phy_interface_mode()
/external/u-boot/drivers/net/phy/
Daquantia.c24 u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_config()
32 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
40 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, in aquantia_config()
56 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
95 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_startup()
Dxilinx_phy.c71 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
120 temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_config()
122 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp); in xilinxphy_config()
Dphy.c142 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_setup_forced()
155 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
165 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_restart_aneg()
195 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
367 u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_parse_link()
798 if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) { in phy_reset()
811 reg = phy_read(phydev, devad, MII_BMCR); in phy_reset()
813 reg = phy_read(phydev, devad, MII_BMCR); in phy_reset()
Det1011c.c30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
Dmarvell.c135 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
143 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
511 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1145_config()
513 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1145_config()
612 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1680_config()
614 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1680_config()
Dmscc.c253 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
254 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (reg_val | BMCR_RESET)); in mscc_phy_soft_reset()
256 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
259 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
Dnatsemi.c21 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
57 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
Dbroadcom.c137 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in bcm5482_config()
139 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in bcm5482_config()
Drealtek.c82 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
128 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211f_config()
Ddavicom.c28 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
Dmv88e61xx.c571 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR); in mv88e61xx_serdes_init()
575 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val); in mv88e61xx_serdes_init()
811 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR); in mv88e61xx_phy_enable()
815 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val); in mv88e61xx_phy_enable()
Dmicrel_ksz90x1.c354 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in ksz9031_config()
356 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr); in ksz9031_config()
/external/u-boot/common/
Dmiiphyutil.c354 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { in miiphy_reset()
358 if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { in miiphy_reset()
372 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { in miiphy_reset()
420 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_speed()
483 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_duplex()
/external/u-boot/arch/arm/mach-davinci/
Dlxt972.c92 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) in lxt972_auto_negotiate()
97 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); in lxt972_auto_negotiate()
/external/u-boot/cmd/
Dmii.c21 { MII_BMCR, "PHY control register" },
198 if ((regno == MII_BMCR) && (pdesc->lo == 6)) { in special_field()
210 else if ((regno == MII_BMCR) && (pdesc->lo == 8)) { in special_field()
/external/u-boot/drivers/net/
Ddavinci_emac.c326 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) in gen_auto_negotiate()
331 davinci_eth_phy_write(phy_addr, MII_BMCR, val); in gen_auto_negotiate()
340 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) in gen_auto_negotiate()
353 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); in gen_auto_negotiate()
Dsmc911x.c87 smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET); in smc911x_phy_configure()
90 smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | in smc911x_phy_configure()
Dax88180.c116 ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE)); in ax88180_phy_reset()
119 while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) { in ax88180_phy_reset()
351 bmcr_val = ax88180_mdio_read (dev, MII_BMCR); in ax88180_media_config()
Dag7xxx.c632 return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000); in ag933x_phy_setup_wan()
658 ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000); in ag933x_phy_setup_lan()
719 return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR, in ag933x_phy_setup_reset_set()
729 ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); in ag933x_phy_setup_reset_fin()
/external/u-boot/board/egnite/ethernut5/
Dethernut5.c174 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET); in board_eth_init()
/external/kernel-headers/original/uapi/linux/
Dmii.h16 #define MII_BMCR 0x00 /* Basic mode control register */ macro
/external/u-boot/drivers/usb/eth/
Dmcs7830.c322 rc = mcs7830_write_phy(udev, MII_BMCR, flg); in mcs7830_set_autoneg()
326 rc = mcs7830_write_phy(udev, MII_BMCR, flg); in mcs7830_set_autoneg()
330 rc = mcs7830_write_phy(udev, MII_BMCR, flg); in mcs7830_set_autoneg()
Dasix.c324 bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR); in mii_nway_restart()
328 asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr); in mii_nway_restart()
405 asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET); in asix_basic_reset()
/external/u-boot/include/linux/
Dmii.h13 #define MII_BMCR 0x00 /* Basic mode control register */ macro

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