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Searched refs:MIN_DELAY_PHASE_1_LIMIT (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_hw_training.h130 #define MIN_DELAY_PHASE_1_LIMIT 0x10 macro
Dddr3_read_leveling.c550 delay = MIN_DELAY_PHASE_1_LIMIT; in ddr3_read_leveling_single_cs_rl_mode()
562 MIN_DELAY_PHASE_1_LIMIT; in ddr3_read_leveling_single_cs_rl_mode()