| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-aliases.s | 179 ; Two 32-bit immediates are encodable by both MOVN and MOVZ, make sure the MOV
196 ; overlaps with MOVZ or MOVN if the repeat-width is the whole register. In
197 ; both cases MOVZ/MOVN are preferred.
222 ; 0xffff is interesting because there are exceptions in the MOVN rules for
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| /external/llvm/test/MC/AArch64/ |
| D | arm64-aliases.s | 179 ; Two 32-bit immediates are encodable by both MOVN and MOVZ, make sure the MOV
196 ; overlaps with MOVZ or MOVN if the repeat-width is the whole register. In
197 ; both cases MOVZ/MOVN are preferred.
222 ; 0xffff is interesting because there are exceptions in the MOVN rules for
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| /external/u-boot/arch/mips/include/asm/ |
| D | asm.h | 182 #define MOVN(rd, rs, rt) \ macro
198 #define MOVN(rd, rs, rt) \ macro
215 #define MOVN(rd, rs, rt) \ macro
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | movw-consts.ll | 52 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
121 ; Mustn't MOVN w0 here.
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| D | arm64-movi.ll | 149 ; Tests for MOVN with MOVK.
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| /external/llvm/test/CodeGen/AArch64/ |
| D | movw-consts.ll | 52 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
121 ; Mustn't MOVN w0 here.
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| D | arm64-movi.ll | 76 ; Tests for MOVN with MOVK.
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 106 #define MOVN 0x92800000 macro
467 return push_inst(compiler, MOVN | RD(dst) | ((~imm & 0xffff) << 5)); in load_immediate()
473 return push_inst(compiler, (MOVN ^ W_OP) | RD(dst) | ((~imm & 0xffff) << 5)); in load_immediate()
475 …return push_inst(compiler, (MOVN ^ W_OP) | RD(dst) | ((~imm & 0xffff0000l) >> (16 - 5)) | (1 << 21… in load_immediate()
491 return push_inst(compiler, MOVN | RD(dst) | ((~imm & 0xffff0000l) >> (16 - 5)) | (1 << 21)); in load_immediate()
493 FAIL_IF(push_inst(compiler, MOVN | RD(dst) | ((~imm & 0xffff) << 5))); in load_immediate()
520 FAIL_IF(push_inst(compiler, MOVN | RD(dst) | ((simm & 0xffff) << 5) | (i << 21))); in load_immediate()
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| D | sljitNativeMIPS_common.c | 195 #define MOVN (HI(0) | LO(11)) macro
1996 ins = MOVN | TA(EQUAL_FLAG); in sljit_emit_cmov()
2004 ins = MOVN | TA(OTHER_FLAG); in sljit_emit_cmov()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 21 def WriteImm : SchedWrite; // MOVN, MOVZ
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| D | AArch64SchedCyclone.td | 131 // MOVN,MOVZ,MOVK
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| D | AArch64InstrInfo.td | 639 defm MOVN : MoveImmediate<0b00, "movn">;
703 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
704 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
706 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
707 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
708 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
709 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
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| D | AArch64SchedFalkorDetails.td | 1235 def : InstRW<[FalkorWr_1XYZB_0cyc], (instregex "^MOVN(W|X)i$")>; // imm fwd
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 21 def WriteImm : SchedWrite; // MOVN, MOVZ
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| D | AArch64SchedCyclone.td | 129 // MOVN,MOVZ,MOVK
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| D | AArch64InstrInfo.td | 443 defm MOVN : MoveImmediate<0b00, "movn">;
507 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
508 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
510 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
511 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
512 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
513 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
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| /external/v8/src/mips/ |
| D | constants-mips.h | 511 MOVN = ((1U << 3) + 3), enumerator
1297 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
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| D | disasm-mips.cc | 1458 case MOVN: in DecodeTypeRegisterSPECIAL()
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 640 MOVN = 0x00000000, enumerator
643 MOVN_w = MoveWideImmediateFixed | MOVN,
644 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
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| D | assembler-arm64.h | 1690 MoveWide(rd, imm, shift, MOVN);
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 493 MOVN = ((1U << 3) + 3), enumerator
1343 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
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| D | disasm-mips64.cc | 1693 case MOVN: in DecodeTypeRegisterSPECIAL()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 605 MOVN = 0x00000000, enumerator
608 MOVN_w = MoveWideImmediateFixed | MOVN,
609 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
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| D | assembler-aarch64.h | 2077 MoveWide(rd, imm, shift, MOVN);
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 794 ### MOVN ### subsection
|