| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | thumbv8m.s | 200 MSR PSP_NS, r2 label
204 MSR CONTROL_NS, r4 label
212 MSR MSPLIM,r8 label
214 MSR PSPLIM,r9 label
219 MSR PSPLIM_NS, r11 label
224 MSR FAULTMASK_NS, r14 label
231 MSR 146, r8 label
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| D | thumbv7m.s | 22 @ MSR
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| D | thumbv7em.s | 10 @ MSR
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| D | thumb2-mclass.s | 38 @ MSR
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| /external/llvm/test/MC/ARM/ |
| D | thumbv8m.s | 200 MSR PSP_NS, r2 label
204 MSR CONTROL_NS, r4 label
212 MSR MSPLIM,r8 label
214 MSR PSPLIM,r9 label
220 MSR PSPLIM_NS, r11 label
229 MSR FAULTMASK_NS, r14 label
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| D | thumbv7m.s | 22 @ MSR
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| D | thumbv7em.s | 10 @ MSR
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| D | thumb2-mclass.s | 38 @ MSR
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | invalid-MSRi-arm.txt | 9 # A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
|
| /external/syzkaller/executor/ |
| D | kvm.S | 154 #define VMSET_LIMITED(FIELD, VAL, MSR) \ argument
155 mov $MSR, %rcx; \
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| /external/llvm/test/CodeGen/AArch64/ |
| D | flags-multiuse.ll | 25 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be
|
| /external/google-breakpad/src/third_party/libdisasm/ |
| D | TODO | 22 * sysenter, sysexit as CALL types -- preceded by MSR writes
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | flags-multiuse.ll | 28 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be
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| /external/u-boot/doc/ |
| D | README.mpc85xx | 7 - MSR[DE] must be set
11 To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrFormats.td | 193 // MSR instruction class in MBlaze : <|opcode|rd|imm15|>
195 class MSR<bits<6> op, bits<6> flags, dag outs, dag ins, string asmstr,
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | int-mul-02.ll | 7 ; Check MSR.
133 ; Check that multiplications of spilled values can use MS rather than MSR.
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | int-mul-02.ll | 7 ; Check MSR.
133 ; Check that multiplications of spilled values can use MS rather than MSR.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-armv7.txt | 246 # A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
506 # Undefined encodings for MSR/MRS (banked register)
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| D | thumb-MSR-MClass.txt | 39 # MSR
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | thumb2-mclass.s | 43 @ MSR
|
| /external/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 26 ; In Thumb mode v7M and v7AR have different MRS/MSR instructions that happen
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-MSR-MClass.txt | 39 # MSR
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 26 ; In Thumb mode v7M and v7AR have different MRS/MSR instructions that happen
|
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| D | isa.hpp | 68 bool MSR(void) { return CPU_Rep.f_1_EDX_[5]; } in MSR() function in InstructionSet
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrHTM.td | 90 // value of the MSR Transaction State (TS) bits that exist before the
|