Searched refs:MUX_MODE10 (Results 1 – 3 of 3) sorted by relevance
54 DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */55 DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
98 DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */99 DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */105 DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */106 DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */
26 #define MUX_MODE10 0xa macro