Searched refs:MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (Results 1 – 14 of 14) sorted by relevance
163 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()
450 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in enable_lvds()538 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in enable_spi_display()
402 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_clock()
463 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_b850v3()511 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display_bx50v3()
478 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display()
400 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); in setup_display()
532 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; in setup_display()
514 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; in setup_display()
592 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()
776 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()
647 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | in setup_display()
714 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()
345 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) macro
452 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; in setup_display()