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Searched refs:NV_PA_PMC_BASE (Results 1 – 15 of 15) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/
Dpowergate.c27 value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); in tegra_powergate_set()
33 writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE); in tegra_powergate_set()
38 value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS); in tegra_powergate_set()
72 writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING); in tegra_powergate_remove_clamping()
Dcpu.c302 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_cpu_powered()
309 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in remove_cpu_io_clamps()
324 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in powerup_cpu()
Dcmd_enterrcm.c34 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in do_enterrcm()
Dap.c153 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in init_pmc_scratch()
Dboard2.c64 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in power_det_init()
Dclock.c817 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in clock_external_output()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dcpu.c23 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail()
114 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in tegra124_init_clocks()
196 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_partition_powered()
206 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in power_partition()
246 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in start_cpu()
/external/u-boot/arch/arm/mach-tegra/tegra114/
Dcpu.c20 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail()
188 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_partition_powered()
198 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_clamp_enabled()
208 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in power_partition()
/external/u-boot/arch/arm/include/asm/arch-tegra/
Dtegra.h33 #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) macro
105 #define PRM_RSTCTRL NV_PA_PMC_BASE
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c648 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
650 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
652 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
654 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
656 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
658 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
Dcpu.c14 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail()
Dwarmboot_avp.c26 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in wb_start()
Dwarmboot.c127 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in warmboot_save_sdram_params()
/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c677 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
679 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
681 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
683 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
685 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
687 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
Dcpu.c50 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail()