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Searched refs:OR2 (Results 1 – 10 of 10) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dand-or-not.ll238 ; CHECK-NEXT: [[OR2:%.*]] = xor i32 [[TMP1]], -1
239 ; CHECK-NEXT: ret i32 [[OR2]]
253 ; CHECK-NEXT: [[OR2:%.*]] = xor i32 [[TMP1]], -1
254 ; CHECK-NEXT: ret i32 [[OR2]]
268 ; CHECK-NEXT: [[OR2:%.*]] = xor i32 [[TMP1]], -1
269 ; CHECK-NEXT: ret i32 [[OR2]]
283 ; CHECK-NEXT: [[OR2:%.*]] = xor i32 [[TMP1]], -1
284 ; CHECK-NEXT: ret i32 [[OR2]]
508 ; CHECK-NEXT: [[OR2:%.*]] = or i64 [[NOTA]], [[C:%.*]]
509 ; CHECK-NEXT: [[AND:%.*]] = and i64 [[OR1]], [[OR2]]
[all …]
Dor-xor.ll315 ; CHECK-NEXT: [[OR2:%.*]] = xor i8 [[XOR]], 8
316 ; CHECK-NEXT: ret i8 [[OR2]]
Dmasked-merge-and-of-ors.ll501 ; CHECK-NEXT: [[OR2:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
502 ; CHECK-NEXT: [[RET:%.*]] = or i32 [[OR2]], -65281
Dicmp.ll2282 ; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHF1]], 1
2283 ; CHECK-NEXT: [[AND3:%.*]] = and i32 [[OR2]], %x
2297 ; CHECK-NEXT: [[OR2:%.*]] = or <2 x i32> [[SHF1]], <i32 1, i32 1>
2298 ; CHECK-NEXT: [[AND3:%.*]] = and <2 x i32> [[OR2]], %x
/external/u-boot/arch/powerpc/cpu/mpc8xx/
DKconfig116 hex "Preliminary value for OR2"
/external/u-boot/arch/powerpc/include/asm/
Dfsl_lbc.h88 #define OR2 0x5014 macro
/external/u-boot/include/
Dppc_asm.tmpl108 #define OR2 0x00000114
/external/llvm/test/Transforms/InstCombine/
Dicmp.ll1633 ; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHF1]], 1
1634 ; CHECK-NEXT: [[AND3:%.*]] = and i32 [[OR2]], %x
/external/u-boot/
DREADME3260 Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart3.csv21537 ,"US","OR2","Orion","Orion","IL","--3-----","RL","1207",,"4121N 09022W",""