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Searched refs:OptionalDef (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrDesc.h39 OptionalDef enumerator
84 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h41 enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef }; enumerator
85 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCInstrDesc.h41 enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef }; enumerator
96 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef()
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/
DMachineInstrTest.cpp110 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}; in TEST()
179 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}; in TEST()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenInstrInfo.inc4310 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
4311 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
4328 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
4337 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
4339 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
4340 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
4341 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
4387 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
4388 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
4389 …dicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp1408 const SDValue &OptionalDef = Node->getOperand(i - Node->getNumValues()); in DelayForLiveRegsBottomUp() local
1409 unsigned Reg = cast<RegisterSDNode>(OptionalDef)->getReg(); in DelayForLiveRegsBottomUp()