Searched refs:PAD_CTL_PUS_PU5KOHM (Results 1 – 5 of 5) sorted by relevance
56 #define GPIO_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \97 #define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU5KOHM)
33 MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |
130 #define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE) macro
47 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
50 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)