/external/u-boot/doc/ |
D | README.srio-pcie-boot-corenet | 2 SRIO and PCIE Boot on Corenet Platforms 5 For some PowerPC processors with SRIO or PCIE interface, boot location can be 6 configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can 8 from another processor's memory space by SRIO or PCIE link connected between 12 platforms and a RCW example with boot from SRIO or PCIE configuration. 14 Environment of the SRIO or PCIE boot: 16 b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and 21 e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set 22 the boot location to SRIO or PCIE, and holdoff all the cores. 27 | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM] [all …]
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/external/u-boot/drivers/phy/marvell/ |
D | comphy_a3700.c | 174 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); in comphy_pcie_power_up() 179 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); in comphy_pcie_power_up() 184 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); in comphy_pcie_power_up() 189 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); in comphy_pcie_power_up() 194 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); in comphy_pcie_power_up() 199 reg_set16(phy_addr(PCIE, MISC_REG0), in comphy_pcie_power_up() 213 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); in comphy_pcie_power_up() 216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); in comphy_pcie_power_up() 222 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, in comphy_pcie_power_up() 229 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); in comphy_pcie_power_up() [all …]
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D | comphy_a3700.h | 74 PCIE = 1, enumerator 80 if (unit == PCIE) in phy_addr()
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/external/u-boot/arch/arm/mach-tegra/tegra30/ |
D | pinmux.c | 263 PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4), 264 PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4), 265 PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4), 266 PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4), 267 PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4), 268 PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4), 269 PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4), 270 PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4), 271 PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4), 272 PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
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/external/u-boot/board/avionic-design/common/ |
D | pinmux-config-tamonten-ng.h | 263 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), 264 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), 265 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), 266 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), 267 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), 268 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), 269 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), 270 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), 271 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), 272 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
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/external/u-boot/board/nvidia/cardhu/ |
D | pinmux-config-cardhu.h | 267 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), 268 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), 269 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), 270 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), 271 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), 272 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), 273 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), 274 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), 275 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), 276 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
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/external/u-boot/board/toradex/colibri_t30/ |
D | pinmux-config-colibri_t30.h | 279 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), 284 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), 285 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), 286 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), 287 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), 288 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), 289 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), 290 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
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/external/u-boot/board/freescale/p1_p2_rdb_pc/ |
D | README | 23 * PCIE slot and mini-PCIE slots
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/external/u-boot/arch/arm/dts/ |
D | zynqmp-zcu102-revA.dts | 153 output-low; /* PCIE = 0, DP = 1 */ 159 output-high; /* PCIE = 0, DP = 1 */ 165 output-high; /* PCIE = 0, USB0 = 1 */ 171 output-high; /* PCIE = 0, SATA = 1 */
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D | am57xx-idk-common.dtsi | 244 /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
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/external/u-boot/board/freescale/c29xpcie/ |
D | README | 34 0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory 37 0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
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/external/u-boot/configs/ |
D | sbc8548_PCI_33_PCIE_defconfig | 8 CONFIG_SYS_EXTRA_OPTIONS="33,PCIE"
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D | sbc8548_PCI_66_PCIE_defconfig | 8 CONFIG_SYS_EXTRA_OPTIONS="66,PCIE"
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/external/u-boot/arch/arm/mach-tegra/tegra20/ |
D | pinmux.c | 304 PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4), 325 PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP), 328 PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
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D | clock.c | 331 NONE(PCIE),
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/external/u-boot/board/toradex/apalis_t30/ |
D | pinmux-config-apalis_t30.h | 295 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), 296 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), 297 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), 298 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
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/external/mesa3d/src/util/xmlpool/ |
D | nl.po | 279 msgid "Only GART (AGP/PCIE) memory (if available)" 280 msgstr "Alleen GART (AGP/PCIE) geheugen (als het aanwezig is)"
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D | sv.po | 271 msgid "Only GART (AGP/PCIE) memory (if available)" 272 msgstr "Endast GART-minne (AGP/PCIE) (om tillgängligt)"
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D | de.po | 282 msgid "Only GART (AGP/PCIE) memory (if available)" 283 msgstr "Nur GART-Speicher (AGP/PCIE) (falls verfügbar)"
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D | fr.po | 278 msgid "Only GART (AGP/PCIE) memory (if available)" 279 msgstr "Utiliser uniquement la mémoire GART (AGP/PCIE) (si disponible)"
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D | es.po | 291 msgid "Only GART (AGP/PCIE) memory (if available)" 292 msgstr "Solo memoria GART (AGP/PCIE) (si está disponible)"
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D | ca.po | 307 msgid "Only GART (AGP/PCIE) memory (if available)" 308 msgstr "Només memòria GART (AGP/PCIE) (si està disponible)"
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/external/u-boot/board/freescale/t4qds/ |
D | README | 107 0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory 111 0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
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/external/u-boot/arch/arm/mach-tegra/tegra114/ |
D | clock.c | 313 NONE(PCIE),
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/external/u-boot/board/hisilicon/poplar/ |
D | README | 18 PCIE One PCIe 2.0 interfaces
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