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Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 11 of 11) sorted by relevance

/external/u-boot/drivers/pinctrl/renesas/
Dpfc-r8a7791.c5710 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5769 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5805 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5841 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5879 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5921 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5959 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5999 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
6040 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6083 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7790.c4952 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4988 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5025 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5054 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5087 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5120 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5157 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5193 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5228 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5269 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7794.c4860 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4914 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4954 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4989 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5029 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5064 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5099 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5145 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5182 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5217 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7792.c2401 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2459 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2517 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2565 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2611 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2652 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2692 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2734 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
Dsh_pfc.h128 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ macro
599 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
Dpfc-r8a77995.c2406 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2438 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Dpfc-r8a7795.c5550 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5575 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5602 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a7796.c5494 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5519 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5546 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a77990.c5096 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5124 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Dpfc-r8a77970.c2354 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
/external/u-boot/include/
Dsh_pfc.h56 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ macro