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Searched refs:PLLE_SS_CNTL_INTERP_RESET (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c624 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
711 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
742 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c653 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
757 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
788 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c938 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
989 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
1033 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c1124 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) macro
1235 value &= ~PLLE_SS_CNTL_INTERP_RESET; in tegra_plle_enable()