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Searched refs:PLLE_SS_CNTL_SSCINC (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/mach-tegra/tegra20/
Dclock.c622 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) macro
738 value &= ~PLLE_SS_CNTL_SSCINC(0xff); in tegra_plle_enable()
739 value |= PLLE_SS_CNTL_SSCINC(0x01); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra30/
Dclock.c651 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) macro
784 value &= ~PLLE_SS_CNTL_SSCINC(0xff); in tegra_plle_enable()
785 value |= PLLE_SS_CNTL_SSCINC(0x01); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dclock.c934 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) macro
1016 value &= ~PLLE_SS_CNTL_SSCINC(0xff); in tegra_plle_enable()
1020 value |= PLLE_SS_CNTL_SSCINC(0x01); in tegra_plle_enable()
/external/u-boot/arch/arm/mach-tegra/tegra210/
Dclock.c1120 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16) macro
1220 value &= ~PLLE_SS_CNTL_SSCINC(0xff); in tegra_plle_enable()
1221 value |= PLLE_SS_CNTL_SSCINC(1); in tegra_plle_enable()