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Searched refs:PPLL_HZ (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rk3399.c53 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
1197 return DIV_TO_RATE(PPLL_HZ, div); in rk3399_i2c_get_pmuclk()
1205 src_clk_div = PPLL_HZ / hz; in rk3399_i2c_set_pmuclk()
1226 return DIV_TO_RATE(PPLL_HZ, src_clk_div); in rk3399_i2c_set_pmuclk()
1237 return DIV_TO_RATE(PPLL_HZ, div); in rk3399_pwm_get_clk()
1247 return PPLL_HZ; in rk3399_pmuclk_get_rate()
1275 return PPLL_HZ; in rk3399_pmuclk_set_rate()
1302 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; in pmuclk_init()
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rk3399.h75 #define PPLL_HZ (676*MHz) macro