| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_post_twiddle_overlap.s | 141 VMULL.S32 Q0, D2, D0
142 VQMOVN.S64 D8, Q0
191 VLD2.32 {Q0, Q1}, [R1], R12
195 VREV64.16 Q0, Q0
251 VMULL.U16 Q0, D26, D18
257 VSHR.U32 Q0, Q0, #16
259 VMLAL.S16 Q0, D27, D18
265 VADD.I32 Q14, Q14, Q0
268 VMULL.U16 Q0, D6, D9
272 VSHR.S32 Q0, Q0, #16
[all …]
|
| D | ia_xheaacd_mps_reoder_mulshift_acc.s | 45 VLD1.32 {Q0, Q1}, [R8]
47 VST1.32 {Q0, Q1}, [R7]
59 VLD1.32 {Q0, Q1}, [R8]! @LOADING values from R0 Sr_fix
69 VMULL.S32 Q0, D4, D12
74 VSHR.S64 Q0, Q0, #31
84 VSUB.I64 Q12, Q12, Q0
103 VLD1.32 {Q0, Q1}, [R8]! @LOADING values from R0 Sr_fix
113 VMULL.S32 Q0, D4, D12
123 VSHR.S64 Q0, Q0, #31
128 VSUB.I64 Q12, Q12, Q0
[all …]
|
| D | ixheaacd_post_twiddle.s | 157 VMULL.U16 Q0, D26, D10
173 VSHR.U32 Q0, Q0, #16
179 VMLAL.S16 Q0, D27, D10
187 VNEG.S32 Q0, Q0
189 VADD.I32 Q13, Q14, Q0
265 VMULL.U16 Q0, D26, D10
281 VSHR.U32 Q0, Q0, #16
287 VMLAL.S16 Q0, D27, D10
295 VNEG.S32 Q0, Q0
297 VADD.I32 Q13, Q14, Q0
[all …]
|
| D | ixheaacd_overlap_add1.s | 51 VQNEG.S32 Q0, Q3
101 VMULL.S32 Q0, D14, D4
102 VQMOVN.S64 D16, Q0
103 VMULL.S32 Q0, D15, D5
104 VQMOVN.S64 D17, Q0
108 VQNEG.S32 Q0, Q3
155 VMULL.S32 Q0, D4, D14
156 VQMOVN.S64 D16, Q0
157 VMULL.S32 Q0, D5, D15
158 VQMOVN.S64 D17, Q0
[all …]
|
| D | ixheaacd_dct3_32.s | 53 VLD1.32 {Q0}, [R6]!
61 VSHR.S32 Q0, Q0, #7
65 VADD.I32 Q2, Q1, Q0
80 VLD1.32 {Q0}, [R6]!
90 VSHR.S32 Q0, Q0, #7
103 VADD.I32 Q2, Q1, Q0
131 VLD1.32 {Q0}, [R6]!
140 VSHR.S32 Q0, Q0, #7
158 VADD.I32 Q2, Q1, Q0
194 VSHR.S32 Q0, Q0, #7
[all …]
|
| D | ixheaacd_esbr_fwd_modulation.s | 40 VSHR.S32 Q0, Q0, #4
51 VQSUB.S32 Q4, Q0, Q2
54 VADD.S32 Q6, Q0, Q2
90 VADD.I64 Q0, Q2, Q5
93 VSHRN.I64 D0, Q0, #31
|
| D | ixheaacd_no_lap1.s | 41 VQNEG.S32 Q0, Q0
45 VQSHL.S32 Q15, Q0, Q1
64 VQNEG.S32 Q0, Q0
72 VQSHL.S32 Q15, Q0, Q1
|
| D | ixheaacd_dec_DCT2_64_asm.s | 45 VLD2.32 {Q0, Q1}, [R0]!
48 VST1.32 {Q0}, [R1]!
85 VLD2.32 {Q0, Q1}, [R0]!
100 VSUB.I32 Q9, Q0, Q2
102 VADD.I32 Q8, Q0, Q2
115 VLD2.32 {Q0, Q1}, [R0]!
147 VSUB.I32 Q9, Q0, Q2
149 VADD.I32 Q8, Q0, Q2
160 VLD2.32 {Q0, Q1}, [R0]!
192 VSUB.I32 Q9, Q0, Q2
[all …]
|
| D | ixheaacd_esbr_cos_sin_mod_loop1.s | 57 VSHRN.I64 D0, Q0, #32
80 VADD.I64 Q0, Q5, Q2
83 VSHRN.I64 D0, Q0, #32
109 VSHRN.I64 D0, Q0, #32
132 VADD.I64 Q0, Q5, Q2
135 VSHRN.I64 D0, Q0, #32
|
| D | ixheaacd_calcmaxspectralline.s | 38 VABS.S32 Q0, Q0
44 VORR Q3, Q0, Q3
|
| D | ixheaacd_pre_twiddle_compute.s | 116 VREV64.16 Q0, Q0
178 VREV64.16 Q0, Q0
244 VREV64.16 Q0, Q0
326 VREV64.16 Q0, Q0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | vldm-liveness.mir | 3 # s1 = VLDRS [r0, 1], implicit-def Q0
4 # s3 = VLDRS [r0, 2], implicit killed Q0, implicit-def Q0
5 # s0 = VLDRS [r0, 0], implicit killed Q0, implicit-def Q0
6 # s2 = VLDRS [r0, 4], implicit killed Q0, implicit-def Q0
10 # imp-use of Q0, which is undefined.
|
| D | 2010-06-29-PartialRedefFastAlloc.ll | 10 ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
11 ; redef, it cannot also get %Q0.
|
| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans_32x32_a9q.s | 224 VADD.S16 Q0, Q4, Q5 @ ee[k] = e[k] + e[16-k] k->1-8 row 1
235 @ Q0 A1 A2 A3 A4 B1 B2 B3 B4
243 VADD.S16 Q13, Q0, Q4 @ eee[k] = ee[k] + ee[7 - k] row 1 & 2
245 VSUB.S16 Q0, Q0 ,Q4 @ eeo[k] = ee[k] - ee[7 - k] row 1 & 2 -- dual issue
401 VMULL.S16 Q0,D2,D4 @eo[4][0-3]* R1
402 VMLAL.S16 Q0,D3,D5 @eo[4][4-7]* R1
453 VTRN.32 Q0, Q5 @ R1
460 VADD.S32 Q0, Q0, Q5 @ R1 -- dual issue
465 VADD.S32 Q9, Q0, Q9 @ R1 -- dual issue
467 VMULL.S16 Q0,D12,D4 @o[0][0-3]* R1
[all …]
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| D | ihevc_sao_edge_offset_class0.s | 190 VCLT.U8 Q0,Q13,Q14 @II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
211 …VSUB.I8 Q10,Q0,Q15 @II sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_g…
215 VCLT.U8 Q0,Q13,Q14 @II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
217 …VSUB.I8 Q11,Q0,Q15 @II sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_…
221 …VMOVL.U8 Q0,D26 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u…
245 …VADDW.S8 Q0,Q0,D30 @II pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[…
248 …VMAX.S16 Q0,Q0,Q2 @II pi2_tmp_cur_row.val[0] = vmaxq_s16(pi2_tmp_cur_row.val…
251 …VMIN.U16 Q0,Q0,Q3 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
253 VMOVN.I16 D0,Q0 @II vmovn_s16(pi2_tmp_cur_row.val[0])
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vldm-liveness.ll | 4 ; s1 = VLDRS [r0, 1], Q0<imp-def>
5 ; s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
6 ; s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
7 ; s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
11 ; imp-use of Q0, which is undefined.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/ |
| D | v65_all.s | 16 if (Q0) vtmp.w=vgather(R0,M0,V0.w).w
36 if (Q0) vtmp.h=vgather(R0,M0,V1:0.w).h
91 if (Q0) vscatter(R0,M0,V1:0.w).h=V0
96 if (Q0) vtmp.h=vgather(R0,M0,V0.h).h
121 if (Q0) vscatter(R0,M0,V0.w).w=V0
131 V0.h=prefixsum(Q0)
141 V0.w=prefixsum(Q0)
146 V0.b=prefixsum(Q0)
161 if (Q0) vscatter(R0,M0,V0.h).h=V0
|
| D | v62_all.s | 15 Q0=vsetq2(R0)
20 Q0.b=vshuffe(Q0.h,Q0.h)
25 Q0.h=vshuffe(Q0.w,Q0.w)
40 V0.w=vadd(V0.w,V0.w,Q0):carry
85 V0=vand(!Q0,R0)
90 V0|=vand(!Q0,R0)
95 V0=vand(!Q0,V0)
100 V0=vand(Q0,V0)
496 V0.w=vsub(V0.w,V0.w,Q0):carry
526 vwhist128(Q0)
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.td | 68 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
70 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
75 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
77 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
110 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
115 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVectorPrint.cpp | 77 || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
88 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
90 return S[R-Hexagon::Q0]; in getStringReg()
192 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()
193 LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n'); in runOnMachineFunction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.td | 72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
74 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
76 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
79 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
81 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
112 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
114 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
116 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
119 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
121 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
82 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
83 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
84 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
94 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
138 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
139 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
141 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
142 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
216 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
82 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
83 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
84 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
94 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
138 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
139 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
141 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
142 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
215 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
|
| /external/deqp-deps/glslang/Test/ |
| D | hlsl.gs-hs-mix.tesc | 95 float4 Q0 = mul(proj_matrix, float4(P0, 1.0));
100 vertex.PositionCS = Q0;
116 vertex.PositionCS = Q0;
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | 2010-06-29-PartialRedefFastAlloc.ll | 10 ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
11 ; redef, it cannot also get %Q0.
|