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Searched refs:R20 (Results 1 – 25 of 67) sorted by relevance

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/external/boringssl/src/crypto/poly1305/
Dpoly1305_vec.c65 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member
110 p->R20.d[1] = (uint32_t)(r0); in CRYPTO_poly1305_init()
111 p->R20.d[3] = (uint32_t)(r0 >> 32); in CRYPTO_poly1305_init()
151 r0 = ((uint64_t)p->R20.d[3] << 32) | (uint64_t)p->R20.d[1]; in poly1305_first_block()
181 p->R20.v = _mm_shuffle_epi32(_mm_cvtsi32_si128((uint32_t)(r20)&0x3ffffff), in poly1305_first_block()
203 p->R20.d[1] = (uint32_t)(r0); in poly1305_first_block()
204 p->R20.d[3] = (uint32_t)(r0 >> 32); in poly1305_first_block()
248 T0 = _mm_mul_epu32(H0, p->R20.v); in poly1305_blocks()
254 T6 = _mm_mul_epu32(H1, p->R20.v); in poly1305_blocks()
273 T5 = _mm_mul_epu32(H2, p->R20.v); in poly1305_blocks()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/
Dzext.ll12 ; zext R25:R24, R20
13 ; mov R24, R20
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaCallingConv.td30 CCIfType<[i64], CCAssignToRegWithShadow<[R16, R17, R18, R19, R20, R21],
34 [R16, R17, R18, R19, R20, R21]>>,
DAlphaRegisterInfo.td58 def R20 : GPR<20, "$20">, DwarfRegNum<[20]>;
115 R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td65 def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>;
96 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>;
117 add R24, R25, R18, R19, R20, R21, R22, R23,
135 add R24, R25, R18, R19, R20, R21, R22, R23,
145 add R23, R22, R21, R20, R19, R18, R17, R16
DAVRCallingConv.td21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td65 def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>;
96 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>;
119 add R24, R25, R18, R19, R20, R21, R22, R23,
137 add R24, R25, R18, R19, R20, R21, R22, R23,
147 add R23, R22, R21, R20, R19, R18, R17, R16
DAVRCallingConv.td21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h125 case MBlaze::R20 : return 20; in getMBlazeRegisterNumbering()
190 case 20 : return MBlaze::R20; in getMBlazeRegisterFromNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeRegisterInfo.cpp49 return MBlaze::R20; in getPICCallReg()
61 MBlaze::R20, MBlaze::R21, MBlaze::R22, MBlaze::R23, in getCalleeSavedRegs()
DMBlazeInstrInfo.cpp292 GlobalBaseReg).addReg(MBlaze::R20); in getGlobalBaseReg()
293 RegInfo.addLiveIn(MBlaze::R20); in getGlobalBaseReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCRegisterInfo.td53 def R20 : Core<20, "%r20">, DwarfRegNum<[20]>;
74 R20, R21, R22, R23, R24, R25, GP, FP, SP, ILINK, R30, BLINK)>;
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.h165 {PPC::R20, -48}, in getCalleeSavedSpillSlots()
244 {PPC::R20, -92}, in getCalleeSavedSpillSlots()
/external/linux-kselftest/tools/testing/selftests/powerpc/stringloops/asm/
Dppc_asm.h21 #define R20 r20 macro
/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/
Dppc_asm.h16 #define R20 r20 macro
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp108 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
117 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h90 case Lanai::R20: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h90 case Lanai::R20: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dbit-cmp0.mir50 # CHECK: %[[R20:[0-9]+]]:intregs = A2_tfrsi 0
51 # CHECK: $r0 = COPY %[[R20]]
Drdf-copy-undef.ll4 ; After a copy R20 = R29, RDF copy propagation attempted to replace R20 with
/external/llvm/test/CodeGen/Mips/
Datomic.ll253 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24
254 ; NO-SEB-SEH: sra $2, $[[R20]], 24
390 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $5, 24
391 ; NO-SEB-SEH: sra $[[R20]], $[[R20]], 24
396 ; NO-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $[[R20]]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h51 case R20: case X20: case F20: case V20: case CR5LT: return 20; in getPPCRegisterNumbering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp106 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
115 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/
Dtwo-extenders.s129 memh(##0x1000) = R20

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