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Searched refs:RD1 (Results 1 – 11 of 11) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/atomics/
Dload16.ll32 ; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
36 ; CHECK-NEXT: st [[RD1]], [[RR1]]
37 ; CHECK-NEXT: std [[RD1]]+1, [[A:r[0-9]+]]
47 ; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
51 ; CHECK-NEXT: st [[RD1]], [[RR1]]
52 ; CHECK-NEXT: std [[RD1]]+1, [[A:r[0-9]+]]
62 ; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
66 ; CHECK-NEXT: st [[RD1]], [[RR1]]
67 ; CHECK-NEXT: std [[RD1]]+1, [[A:r[0-9]+]]
77 ; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
[all …]
/external/llvm/test/CodeGen/Mips/msa/
Delm_copy.ll100 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
105 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
198 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
203 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Delm_copy.ll100 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
105 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
198 ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2]
203 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
/external/u-boot/arch/arm/dts/
Dsama5d3_gmac.dtsi44 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
54 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
Dsama5d3.dtsi805 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
Dsama5d4.dtsi1793 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
/external/clang/lib/Sema/
DSemaChecking.cpp10559 RecordDecl *RD1, in isLayoutCompatibleStruct() argument
10562 if (const CXXRecordDecl *D1CXX = dyn_cast<CXXRecordDecl>(RD1)) { in isLayoutCompatibleStruct()
10589 Field1 = RD1->field_begin(), in isLayoutCompatibleStruct()
10590 Field1End = RD1->field_end(); in isLayoutCompatibleStruct()
10604 RecordDecl *RD1, in isLayoutCompatibleUnion() argument
10610 for (auto *Field1 : RD1->fields()) { in isLayoutCompatibleUnion()
10630 bool isLayoutCompatible(ASTContext &C, RecordDecl *RD1, RecordDecl *RD2) { in isLayoutCompatible() argument
10631 if (RD1->isUnion() != RD2->isUnion()) in isLayoutCompatible()
10634 if (RD1->isUnion()) in isLayoutCompatible()
10635 return isLayoutCompatibleUnion(C, RD1, RD2); in isLayoutCompatible()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3114 unsigned RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() local
3115 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) in emitMSACBranchPseudo()
3127 .addReg(RD1) in emitMSACBranchPseudo()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3023 unsigned RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() local
3024 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) in emitMSACBranchPseudo()
3036 .addReg(RD1) in emitMSACBranchPseudo()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dparam-load-store.ll784 ; CHECK-DAG: ld.param.u64 [[RD1:%rd[0-9]+]], [test_s_i32x4_param_0+16];
/external/libxml2/result/HTML/
Ddoc3.htm.sax1849 SAX.characters(RD1 BIOS Savior, 15)