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Searched refs:REG_DRAM_TRAINING_2_FIFO_RST_OFFS (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_read_leveling.c299 (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS); in ddr3_read_leveling_sw()
305 (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS); in ddr3_read_leveling_sw()
446 (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS); in ddr3_read_leveling_single_cs_rl_mode()
452 (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS); in ddr3_read_leveling_single_cs_rl_mode()
800 (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS); in ddr3_read_leveling_single_cs_window_mode()
806 (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS); in ddr3_read_leveling_single_cs_window_mode()
Dddr3_sdram.c649 reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) + in ddr3_reset_phy_read_fifo()
658 (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS); in ddr3_reset_phy_read_fifo()
Dddr3_axp.h233 #define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4 macro
Dddr3_pbs.c680 reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) in ddr3_pbs_rx()
688 & (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS); in ddr3_pbs_rx()
Dddr3_hw_training.c930 reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) + in ddr3_training_suspend_resume()