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Searched refs:REG_SEQUENCE (Results 1 – 25 of 158) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dfold-immediate-output-mods.mir53 %28 = REG_SEQUENCE %3, 1, %27, 2
56 %13 = REG_SEQUENCE killed %12, 1, killed %11, 2
57 %14 = REG_SEQUENCE killed %5, 17, %13, 18
60 %17 = REG_SEQUENCE killed %6, 17, %13, 18
61 %18 = REG_SEQUENCE killed %4, 17, %13, 18
124 %28 = REG_SEQUENCE %3, 1, %27, 2
127 %13 = REG_SEQUENCE killed %12, 1, killed %11, 2
128 %14 = REG_SEQUENCE killed %5, 17, %13, 18
131 %17 = REG_SEQUENCE killed %6, 17, %13, 18
132 %18 = REG_SEQUENCE killed %4, 17, %13, 18
[all …]
Dclamp-omod-special-case.mir49 %25 = REG_SEQUENCE %3, 1, %24, 2
52 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
53 %13 = REG_SEQUENCE killed %5, 17, %12, 18
56 %16 = REG_SEQUENCE killed %4, 17, %12, 18
111 %25 = REG_SEQUENCE %3, 1, %24, 2
114 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
115 %13 = REG_SEQUENCE killed %5, 17, %12, 18
118 %16 = REG_SEQUENCE killed %4, 17, %12, 18
174 %25 = REG_SEQUENCE %3, 1, %24, 2
177 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
[all …]
Dshrink-vop3-carry-out.mir77 %27 = REG_SEQUENCE %3, 1, %26, 2
80 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
81 %13 = REG_SEQUENCE killed %5, 17, %12, 18
83 %16 = REG_SEQUENCE killed %4, 17, %12, 18
161 %27 = REG_SEQUENCE %3, 1, %26, 2
164 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
165 %13 = REG_SEQUENCE killed %5, 17, %12, 18
167 %16 = REG_SEQUENCE killed %4, 17, %12, 18
245 %27 = REG_SEQUENCE %3, 1, %26, 2
248 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
[all …]
Dopt-sgpr-to-vgpr-copy.mir8 # GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[…
15 # GCN-NEXT: %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], %subreg.sub0, killed %[[…
20 # GCN: %[[OP0:[0-9]+]]:vreg_64 = REG_SEQUENCE killed %{{[0-9]+}}, %subreg.sub0, killed %{{[0-…
112 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1
120 %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1
123 %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1
136 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1
137 %28 = REG_SEQUENCE %6, 17, killed %27, 18
211 %11 = REG_SEQUENCE %2, %subreg.sub0, killed %10, %subreg.sub1
219 %18 = REG_SEQUENCE killed %16, %subreg.sub0, killed %17, %subreg.sub1
[all …]
Ddetect-dead-lanes.mir9 # CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub3
31 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
45 # CHECK: %0:sreg_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2
90 %0 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2
128 # CHECK: %3:sreg_128 = REG_SEQUENCE undef %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
134 # CHECK: %6:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1
149 # CHECK: %15:sreg_128 = REG_SEQUENCE %13, %subreg.sub0_sub1, undef %14, %subreg.sub2_sub3
177 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
183 %6 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1
198 %15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3
[all …]
Dsdwa-scalar-ops.mir222 %16 = REG_SEQUENCE %14, 1, %15, 2
230 %67 = REG_SEQUENCE %70, 1, killed %65, 2
236 %41 = REG_SEQUENCE killed %71, 1, killed %72, 2
242 %80 = REG_SEQUENCE %83, 1, killed %78, 2
246 %57 = REG_SEQUENCE %55, 1, killed %56, 2
385 %16 = REG_SEQUENCE %14, 1, %15, 2
393 %67 = REG_SEQUENCE %70, 1, killed %65, 2
399 %41 = REG_SEQUENCE killed %71, 1, killed %72, 2
405 %80 = REG_SEQUENCE %83, 1, killed %78, 2
409 %57 = REG_SEQUENCE %55, 1, killed %56, 2
Dconstant-fold-imm-immreg.mir52 %6 = REG_SEQUENCE killed %2, 1, killed %3, 2, killed %4, 3, killed %5, 4
135 %32 = REG_SEQUENCE %3, 1, %31, 2
141 %37 = REG_SEQUENCE %44, 1, killed %35, 2
219 %10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
321 %16 = REG_SEQUENCE %2, 1, %15, 2
327 %20 = REG_SEQUENCE %21, 1, killed %18, 2
419 %10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
524 %16 = REG_SEQUENCE %2, 1, %15, 2
530 %20 = REG_SEQUENCE %21, 1, killed %18, 2
627 %10 = REG_SEQUENCE killed %7, 1, killed %6, 2, killed %9, 3, killed %8, 4
[all …]
Dfold-imm-f16-f32.mir160 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
224 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
291 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
362 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
429 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
496 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
566 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
633 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
699 %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
Dsgpr-copy-duplicate-operand.ll5 ; used in an REG_SEQUENCE that also needs to be handled.
/external/llvm/test/CodeGen/AMDGPU/
Ddetect-dead-lanes.mir19 # CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
42 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
56 # CHECK: %0 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}}
102 %0 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2
140 # CHECK: %3 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}}
146 # CHECK: %6 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}}
161 # CHECK: %15 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
190 %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
196 %6 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1
211 %15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3
[all …]
Dsgpr-copy-duplicate-operand.ll5 ; used in an REG_SEQUENCE that also needs to be handled.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-constant.mir25 ; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO0]], %subreg.sub0, [[HI0]], %subreg.sub1
33 ; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO1]], %subreg.sub0, [[HI1]], %subreg.sub1
41 ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO2]], %subreg.sub0, [[HI2]], %subreg.sub1
49 ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO3]], %subreg.sub0, [[HI3]], %subreg.sub1
Dinst-select-load-smrd.mir47 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
54 # SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %s…
61 # GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
68 # GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %su…
79 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
86 # SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %s…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dregbankselect-reg_sequence.mir7 # Check that we produce a valid mapping for REG_SEQUENCE.
10 # whereas since REG_SEQUENCE are kind of target opcode
23 %0 = REG_SEQUENCE $d0, %subreg.dsub0, $d1, %subreg.dsub1
/external/llvm/test/CodeGen/MIR/X86/
Dsubregister-index-operands.mir17 # CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}}
29 %ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/AMDGPU/
Dmir-canon-multi.mir18 %27:vreg_64 = REG_SEQUENCE %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1
23 …%16:sgpr_128 = REG_SEQUENCE killed %vreg123_0, %subreg.sub0, %vreg123_1, %subreg.sub1, %vreg123_2,…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/X86/
Dsubregister-index-operands.mir27 …; CHECK: $ax = REG_SEQUENCE [[EXTRACT_SUBREG]], %subreg.sub_8bit, [[EXTRACT_SUBREG]], %subreg.sub_…
31 $ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
/external/llvm/include/llvm/Target/
DTargetOpcodes.def75 /// REG_SEQUENCE - This variadic instruction is used to form a register that
80 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
83 /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
86 HANDLE_TARGET_OPCODE(REG_SEQUENCE, 12)
/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp148 case TargetOpcode::REG_SEQUENCE: in lowersToCopies()
174 case TargetOpcode::REG_SEQUENCE: { in isCrossCopy()
243 case TargetOpcode::REG_SEQUENCE: { in transferUsedLanes()
318 case TargetOpcode::REG_SEQUENCE: { in transferDefinedLanes()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetOpcodes.h81 REG_SEQUENCE = 12, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DDetectDeadLanes.cpp146 case TargetOpcode::REG_SEQUENCE: in lowersToCopies()
172 case TargetOpcode::REG_SEQUENCE: { in isCrossCopy()
241 case TargetOpcode::REG_SEQUENCE: { in transferUsedLanes()
316 case TargetOpcode::REG_SEQUENCE: { in transferDefinedLanes()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dcext-unnamed-global.mir31 %2:doubleregs = REG_SEQUENCE %0, %subreg.isub_lo, %1, %subreg.isub_hi
Dswp-dead-regseq.ll4 ; Check that a dead REG_SEQUENCE doesn't ICE.
/external/llvm/test/CodeGen/ARM/
D2012-01-24-RegSequenceLiveRange.ll7 ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
D2012-01-24-RegSequenceLiveRange.ll7 ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.

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