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Searched refs:RL (Results 1 – 25 of 295) sorted by relevance

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/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart3.csv2 "+","OM","ALA","Al Azaiba","Al Azaiba","MA","--3-----","RL","1301",,"2336S 05832E",
5 ,"OM","DQM","Duqm","Duqm","WU","1-3-----","RL","1207",,"1939N 05742E",
6 ,"OM","FAH","Fahal","Fahal","MA","1-------","RL","0212",,"2341N 05830E",
10 ,"OM","MFH","Mina' al Fahl","Mina' al Fahl","MA","1-------","RL","0212",,"2338N 05831E",
11 ,"OM","MNQ","Mina' Qabus","Mina' Qabus","MA","--3-----","RL","0212",,"2337N 05834E",
12 ,"OM","STQ","Mina Sultan Qaboos, Muscat","Mina Sultan Qaboos, Muscat",,"1-3-----","RL","0607",,"233…
17 ,"OM","QAL","Qalhat","Qalhat","SH","1-3-----","RL","0307",,"2242N 05922E",
20 ,"OM","RUS","Rusayl","Rusayl","MA","--3-----","RL","0701",,"2332N 05811E",
23 ,"OM","SEE","Seeb","Seeb",,"--3-----","RL","0201",,"2335N 05817E",
29 ,"PA","ABA","Agua Buena","Agua Buena",,"--3--6--","RL","0607",,"0735N 08017W",
[all …]
D2013-1_UNLOCODE_CodeListPart1.csv3 ,"AD","CAN","Canillo","Canillo",,"--3-----","RL","0307",,"4234N 00135E",
4 ,"AD","ENC","Encamp","Encamp",,"--3-----","RL","0307",,"4232N 00134E",
5 ,"AD","ESC","Escaldes-Engordany","Escaldes-Engordany",,"--3-----","RL","0307",,"4231N 00133E",
7 ,"AD","LMA","La Massana","La Massana",,"--3-----","RL","0307",,"4234N 00129E",
8 ,"AD","ORD","Ordino","Ordino",,"--3-----","RL","0307",,"4233N 00131E",
9 ,"AD","PAS","Pas de la Casa","Pas de la Casa",,"--3----B","RL","0307",,"4233N 00144E",
10 ,"AD","SJL","Sant Juli� de L�ria","Sant Julia de Loria",,"--3-----","RL","1101",,"4228N 00130E",""
11 ,"AD","SCO","Santa Coloma","Santa Coloma",,"--3-----","RL","0307",,"4230N 00130E",
13 ,"AE","ABU","Abu al Bukhoosh","Abu al Bukhoosh",,"1-------","RL","0307",,"2529N 05308E",
15 ,"AE","AMU","Abu Musa","Abu Musa",,"1-------","RL","0201",,"2552N 05501E",
[all …]
D2013-1_UNLOCODE_CodeListPart2.csv4 ,"GA","BEL","Belleville","Belleville",,"--3-----","RL","0607",,"0002N 01102E",
10 ,"GA","CCB","Cocobeach","Cocobeach",,"1-------","RL","9811",,,
11 ,"GA","EKU","Equata","Equata","1","1-------","RL","0212",,"0013S 00918E",
18 ,"GA","KOU","Koulamoutou","Koulamoutou",,"--34----","RL","0212",,"0107S 01230E",
28 ,"GA","MBA","Mayumba","Mayumba","05","-----6--","RL","0901",,"0259N 01017E",
40 ,"GA","MVE","Mvengu�","Mvengue",,"--3-----","RL","0201",,"0139S 01323E",
45 ,"GA","OGU","Oguandjo Terminal","Oguandjo Terminal",,"1-------","RL","0901",,"0130S 00854E",
56 ,"GA","WNE","Wora Na Ye","Wora Na Ye",,"--34----","RL","0907",,"0221S 00920E",
58 ,"GB","BYS","Abbeystead","Abbeystead","LAN","-----6--","RL","1201",,"5358N 00240W",
59 ,"GB","ASB","Abbots Bromley","Abbots Bromley","STS","--3-----","RL","0201",,"5249N 00153W",
[all …]
/external/tensorflow/tensorflow/python/debug/cli/
Dstepper_cli.py31 RL = debugger_cli_common.RichLine variable
263 node_prefix = RL(" ") + RL(self.NEXT_NODE_POINTER_STR, "bold")
265 node_prefix = RL(" ")
335 status = RL()
338 status += (RL(self.STATE_IS_PLACEHOLDER,
341 status += (RL(self.STATE_UNFEEDABLE,
345 status += (RL(self.STATE_CONT, self._STATE_COLORS[self.STATE_CONT])
350 status += (RL(self.STATE_DUMPED_INTERMEDIATE,
357 status += (RL(self.STATE_OVERRIDDEN,
360 status += (RL(self.STATE_DIRTY_VARIABLE,
[all …]
Dcurses_widgets.py23 RL = debugger_cli_common.RichLine variable
177 output = RL("| ")
178 output += RL(
182 output += RL(" ")
183 output += RL(
192 output += RL(" | ")
194 output += RL("(-%d) " % (len(self._items) - 1 - self._pointer),
200 output += RL(maybe_truncated_command, command_attribute)
Dprofile_analyzer_cli.py34 RL = debugger_cli_common.RichLine variable
131 return RL(text, font_attr=menu_item)
534 output = [RL("-" * screen_cols)]
537 output.append(RL(device_row))
538 output.append(RL())
542 row = RL()
550 row += RL(column_name, font_attr=[head_menu_item, "bold"])
551 row += RL(" " * (column_widths[col] - len(column_name)))
557 new_row = RL()
566 new_row += RL(" " * (column_widths[col] - len(new_cell)))
[all …]
Dcli_config.py27 RL = debugger_cli_common.RichLine variable
139 lines = [RL("Command-line configuration:", "bold"), RL("")]
142 line = RL(" ")
143 line += RL(name, ["underline", highlight_attr])
144 line += RL(": ")
145 line += RL(str(val), font_attr=highlight_attr)
Dcli_shared.py33 RL = debugger_cli_common.RichLine variable
230 RL("ERROR: " + msg, COLOR_RED)])
255 lines = [RL(indent_str) + RL(command, font_attr) + ":",
363 more_lines.append(RL(" * ") + RL(filter_name, command_menu_node))
379 out.append_rich_line(RL("For more details, see ") +
380 RL("help.", debugger_cli_common.MenuItem("", "help")) +
461 RL("!!! An error occurred during the run !!!", "blink"),
Danalyzer_cli.py41 RL = debugger_cli_common.RichLine variable
852 lines = [RL(""), RL(""), RL("Traceback of node construction:", "bold")]
862 line_number_line = RL(" ")
863 line_number_line += RL("Line: %d" % line, attribute)
1130 annotated_line = RL("L%d" % (i + 1), cli_shared.COLOR_YELLOW)
1142 omitted_info_line = RL(" (... Omitted %d of %d %s ...) " % (
1146 omitted_info_line += RL(
1155 label = RL(" " * 4)
1162 label += RL(element, attribute)
1194 lines = [RL("TensorFlow Python library file(s):", color)]
[all …]
/external/compiler-rt/test/tsan/
Ddeadlock_detector_stress_test.cc129 void RL(size_t i) { in RL() function in LockTest
284 RL(0); L(1); RU(0); U(1); in Test8()
285 L(1); RL(0); RU(0); U(1); in Test8()
290 RL(2); RL(3); RU(2); RU(3); in Test8()
291 RL(3); RL(2); RU(2); RU(3); in Test8()
374 RL(000); in Test12_Thread()
375 RL(100); in Test12_Thread()
376 RL(200); in Test12_Thread()
377 RL(300); in Test12_Thread()
397 RL(0); in Test13_Thread()
[all …]
/external/clang/lib/StaticAnalyzer/Checkers/
DPaddingChecker.cpp79 const ASTRecordLayout &RL = ASTContext.getASTRecordLayout(RD); in visitRecord() local
80 assert(llvm::isPowerOf2_64(RL.getAlignment().getQuantity())); in visitRecord()
82 CharUnits BaselinePad = calculateBaselinePad(RD, ASTContext, RL); in visitRecord()
85 CharUnits OptimalPad = calculateOptimalPad(RD, ASTContext, RL); in visitRecord()
168 const ASTRecordLayout &RL) { in calculateBaselinePad() argument
170 CharUnits Offset = ASTContext.toCharUnitsFromBits(RL.getFieldOffset(0)); in calculateBaselinePad()
177 auto FieldOffsetBits = RL.getFieldOffset(FD->getFieldIndex()); in calculateBaselinePad()
182 PaddingSum += RL.getSize() - Offset; in calculateBaselinePad()
204 const ASTRecordLayout &RL) { in calculateOptimalPad() argument
234 CharUnits NewOffset = ASTContext.toCharUnitsFromBits(RL.getFieldOffset(0)); in calculateOptimalPad()
[all …]
/external/u-boot/drivers/ddr/microchip/
Dddr2.c38 writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) | in ddr2_phy_init()
168 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); in ddr2_ctrl_init()
177 (((RL + 5) >> 4) << 29) | in ddr2_ctrl_init()
186 ((RL + 3) << 28)), &ctrl->dlycfg2); in ddr2_ctrl_init()
196 writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), in ddr2_ctrl_init()
228 host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24), in ddr2_ctrl_init()
241 host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24), in ddr2_ctrl_init()
/external/llvm/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
15 store i64 %tmp1617, i64* %RL
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
34 store i64 %tmp1617, i64* %RL
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
15 store i64 %tmp1617, i64* %RL
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
34 store i64 %tmp1617, i64* %RL
/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
15 store i64 %tmp1617, i64* %RL
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
34 store i64 %tmp1617, i64* %RL
/external/autotest/client/site_tests/firmware_TouchMTB/
Dtest_conf.py420 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
426 GV.RL: ('horizontal', 'from right to left',),
475 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
482 GV.RL: ('horizontal', 'from right to left',),
508 variations=((GV.LR, GV.RL, GV.TB, GV.BT, GV.BLTR, GV.TRBL),
516 GV.RL: ('from right to left', 'below the stationary finger'),
721 variations=(GV.LR, GV.RL, GV.TB, GV.BT),
726 GV.RL: ('bottom edge', 'from right to left', 'above'),
744 variations=(GV.LR, GV.RL, GV.TB, GV.BT),
749 GV.RL: ('horizontally from right to left',),
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Daddsub-i128.ll6 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
18 store i64 %tmp1617, i64* %RL
25 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
37 store i64 %tmp1617, i64* %RL
/external/v8/tools/release/
Dtest_scripts.py246 def RL(text, cb=None): function
446 RL("Y"),
458 RL("n"),
469 RL("Y"),
599 RL(""), # Open editor.
792 expectations.append(RL("")) # Open editor.
810 expectations.append(RL("Y")) # Sanity check.
1203 RL("Y"), # Automatically add corresponding ports (ab34567, ab56789)?
1238 RL("Y"), # Automatically increment patch level?
1240 RL("reviewer@chromium.org"), # V8 reviewer.
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonBlockRanges.cpp74 void HexagonBlockRanges::RangeList::include(const RangeList &RL) { in include() argument
75 for (auto &R : RL) in include()
389 RangeList &RL = F->second; in computeDeadMap() local
390 RangeList::iterator A = RL.begin(), Z = RL.end()-1; in computeDeadMap()
461 const HexagonBlockRanges::RangeList &RL) { in operator <<() argument
462 for (auto &R : RL) in operator <<()
479 const HexagonBlockRanges::RangeList &RL = I.second; in operator <<() local
480 OS << PrintReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; in operator <<()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonBlockRanges.cpp76 void HexagonBlockRanges::RangeList::include(const RangeList &RL) { in include() argument
77 for (auto &R : RL) in include()
443 RangeList &RL = F->second; in computeDeadMap() local
444 RangeList::iterator A = RL.begin(), Z = RL.end()-1; in computeDeadMap()
515 const HexagonBlockRanges::RangeList &RL) { in operator <<() argument
516 for (auto &R : RL) in operator <<()
533 const HexagonBlockRanges::RangeList &RL = I.second; in operator <<() local
534 OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; in operator <<()
/external/clang/lib/CodeGen/
DCGRecordLayoutBuilder.cpp713 CGRecordLayout *RL = in ComputeRecordLayout() local
717 RL->NonVirtualBases.swap(Builder.NonVirtualBases); in ComputeRecordLayout()
718 RL->CompleteObjectVirtualBases.swap(Builder.VirtualBases); in ComputeRecordLayout()
721 RL->FieldInfo.swap(Builder.Fields); in ComputeRecordLayout()
724 RL->BitFields.swap(Builder.BitFields); in ComputeRecordLayout()
732 RL->print(llvm::outs()); in ComputeRecordLayout()
756 dyn_cast<llvm::StructType>(RL->getLLVMType()); in ComputeRecordLayout()
767 unsigned FieldNo = RL->getLLVMFieldNo(FD); in ComputeRecordLayout()
781 const CGBitFieldInfo &Info = RL->getBitFieldInfo(FD); in ComputeRecordLayout()
782 llvm::Type *ElementTy = ST->getTypeAtIndex(RL->getLLVMFieldNo(FD)); in ComputeRecordLayout()
[all …]
DCGObjCRuntime.cpp41 const ASTRecordLayout *RL; in LookupFieldBitOffset() local
43 RL = &CGM.getContext().getASTObjCImplementationLayout(ID); in LookupFieldBitOffset()
45 RL = &CGM.getContext().getASTObjCInterfaceLayout(Container); in LookupFieldBitOffset()
60 assert(Index < RL->getFieldCount() && "Ivar is not inside record layout!"); in LookupFieldBitOffset()
62 return RL->getFieldOffset(Index); in LookupFieldBitOffset()
/external/u-boot/arch/arm/mach-omap2/omap4/
Demif.c25 .RL = 6,
49 .RL = 3,
Dsdram_elpida.c192 .RL = 6,
215 .RL = 5,
238 .RL = 3,
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dmisched-fusion-addr.ll57 ; CHECK: adrp [[RL:x[0-9]+]], var_64bit
58 ; CHECK-NEXT: str {{x[0-9]+}}, {{\[}}[[RL]], {{#?}}:lo12:var_64bit{{\]}}
69 ; CHECK: adrp [[RL:x[0-9]+]], var_64bit
70 ; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[RL]], {{#?}}:lo12:var_64bit{{\]}}

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