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Searched refs:RLDICL (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td1332 dag LE_HALF_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 48), sub_32));
1333 dag LE_HALF_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 48), sub_32));
1334 dag LE_HALF_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 48), sub_32));
1335 dag LE_HALF_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 48), sub_32));
1336 dag LE_HALF_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 48), sub_32));
1337 dag LE_HALF_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 48), sub_32));
1338 dag LE_HALF_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 48), sub_32));
1339 dag LE_HALF_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 48), sub_32));
1342 dag LE_BYTE_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 56), sub_32));
1343 dag LE_BYTE_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 56, 56), sub_32));
[all …]
DPPCInstrHTM.td170 (RLDICL (i64 (COPY (TABORTWCI 0, ZERO, 0))), 36, 28)>;
DPPCInstr64Bit.td715 defm RLDICL : MDForm_1r<30, 0,
1183 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1234 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1240 (RLDICL $in, imm:$imm, 0)>;
DPPCInstrInfo.td3078 (RLDICL (CNTLZD $in), 58, 63)> >;
3086 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3094 (RLDICL $in, 1, 63)> >;
3102 (RLDICL (i64not $in), 1, 63)> >;
3110 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3118 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3126 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3134 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3142 (RLDICL (i64not $in), 1, 63)> >;
3150 (RLDICL $in, 1, 63)> >;
[all …]
DPPCISelDAGToDAG.cpp1493 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0); in SelectRotMask64()
2639 CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops); in Select()
4114 if (N->getMachineOpcode() != PPC::RLDICL) in PeepholePPC64ZExt()
DPPCFrameLowering.cpp931 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) in emitPrologue()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dconvert-rr-to-ri-instrs-out-of-range.mir372 %9 = RLDICL killed %7, 0, 32
430 %6 = RLDICL killed %3, 0, 32
551 %9 = RLDICL killed %7, 0, 32
671 %9 = RLDICL killed %7, 0, 32
838 ; CHECK: RLDICL %0, 12, 0
890 %2 = RLDICL %1, 0, 58
1000 %2 = RLDICL %1, 0, 58
1162 ; CHECK: RLDICL %0, 48, 16
Dlivephysregs.mir23 $x3 = RLDICL killed $x3, 0, 48
Dconvert-rr-to-ri-instrs.mir1953 %10 = RLDICL killed %8, 0, 32
2016 %10 = RLDICL killed %8, 0, 32
2082 %6 = RLDICL killed %4, 0, 32
2159 %6 = RLDICL killed %4, 0, 32
2166 %11 = RLDICL killed %9, 0, 32
2566 %16 = RLDICL killed %14, 0, 32
2645 %16 = RLDICL killed %14, 0, 32
3667 ; CHECK: RLDICL %0, 14, 0
3719 %2 = RLDICL %1, 0, 58
3829 %2 = RLDICL %1, 0, 58
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1817 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0); in SelectRotMask64()
2519 PPC::RLDICL, dl, InVT, InputOp, in computeLogicOpInGPR()
2681 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, in getCompoundZeroComparisonInGPR()
2698 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, in getCompoundZeroComparisonInGPR()
2801 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Sub, in get32BitZExtCompare()
2824 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, in get32BitZExtCompare()
2860 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, in get32BitZExtCompare()
2878 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, in get32BitZExtCompare()
2897 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, in get32BitZExtCompare()
2983 SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, in get32BitSExtCompare()
[all …]
DPPCInstrHTM.td170 (RLDICL (i64 (COPY (TABORTWCI 0, ZERO, 0))), 36, 28)>;
DPPCInstrVSX.td1602 dag LE_HALF_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 48), sub_32));
1603 dag LE_HALF_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 48), sub_32));
1604 dag LE_HALF_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 48), sub_32));
1605 dag LE_HALF_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 48), sub_32));
1606 dag LE_HALF_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 48), sub_32));
1607 dag LE_HALF_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 48), sub_32));
1608 dag LE_HALF_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 48), sub_32));
1609 dag LE_HALF_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 48), sub_32));
1612 dag LE_BYTE_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 56), sub_32));
1613 dag LE_BYTE_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 56, 56), sub_32));
[all …]
DPPCInstrInfo.cpp1928 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) { in optimizeCompareInstr()
2296 Opc == PPC::RLDICL || Opc == PPC::RLDICLo || in getConstantDefMI()
2485 case PPC::RLDICL: in convertToImmediateForm()
2492 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ? in convertToImmediateForm()
2766 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
2772 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
3147 if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33) in isSignExtendingOp()
3174 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo || in isZeroExtendingOp()
DPPCMIPeephole.cpp144 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo || in getKnownLeadingZeroCount()
627 case PPC::RLDICL: { in simplifyCode()
DPPCInstrInfo.td3362 (RLDICL (CNTLZD $in), 58, 63)> >;
3370 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
3378 (RLDICL $in, 1, 63)> >;
3386 (RLDICL (i64not $in), 1, 63)> >;
3394 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
3402 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
3410 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3418 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
3426 (RLDICL (i64not $in), 1, 63)> >;
3434 (RLDICL $in, 1, 63)> >;
[all …]
DPPCInstr64Bit.td830 defm RLDICL : MDForm_1r<30, 0,
1333 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1388 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1394 (RLDICL $in, imm:$imm, 0)>;
DPPCFrameLowering.cpp944 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) in emitPrologue()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstr64Bit.td464 def RLDICL : MDForm_1<30, 0,
683 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
725 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
731 (RLDICL G8RC:$in, imm:$imm, 0)>;
DPPCFrameLowering.cpp393 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) in emitPrologue()
/external/v8/src/ppc/
Ddisasm-ppc.cc1099 case RLDICL: { in DecodeExt5()
Dassembler-ppc.cc378 ((EXT5 | (instr & kExt5OpcodeMask)) == RLDICL)); in IsRldicl()
1148 md_form(EXT5 | RLDICL, ra, rs, sh, mb, r); in rldicl()
Dconstants-ppc.h2506 V(rldicl, RLDICL, 0x78000000) \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp1118 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo); in ProcessInstruction()
1144 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo); in ProcessInstruction()
1177 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo); in ProcessInstruction()
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp1064 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo); in ProcessInstruction()
1090 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo); in ProcessInstruction()
1114 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo); in ProcessInstruction()
/external/pcre/dist2/src/sljit/
DsljitNativePPC_64.c121 (RLDICL | S(src) | A(dst) | ((from) << 6) | (1 << 5))

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