/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.td | 4121 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4123 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4126 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4128 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4132 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4135 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4148 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4150 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4152 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4157 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), [all …]
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D | ARMInstrThumb2.td | 561 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 563 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 2819 def : Thumb2DSPPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2820 (t2SMLALBB $Rn, $Rm, $RLo, $RHi)>; 2821 def : Thumb2DSPPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2822 (t2SMLALBT $Rn, $Rm, $RLo, $RHi)>; 2823 def : Thumb2DSPPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2824 (t2SMLALTB $Rn, $Rm, $RLo, $RHi)>; 2825 def : Thumb2DSPPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2826 (t2SMLALTT $Rn, $Rm, $RLo, $RHi)>; [all …]
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenMCPseudoLowering.inc | 136 // Operand: RLo 236 // Operand: RLo
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D | ARMGenDAGISel.inc | 29231 /* 63936*/ OPC_RecordChild2, // #2 = $RLo 29239 …] }:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$RLo, GPR:{ *:[i32] }:$R… 29240 …*:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$Rn, ?:{ *:[i32] }:$Rm, ?:{ *:[i32] }:$RLo, ?:{ *:[i32] }:$RHi) 29247 …] }:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$RLo, GPR:{ *:[i32] }:$R… 29248 …*:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$Rn, ?:{ *:[i32] }:$Rm, ?:{ *:[i32] }:$RLo, ?:{ *:[i32] }:$RHi) 29253 /* 63989*/ OPC_RecordChild2, // #2 = $RLo 29261 …] }:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$RLo, GPR:{ *:[i32] }:$R… 29262 …*:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$Rn, ?:{ *:[i32] }:$Rm, ?:{ *:[i32] }:$RLo, ?:{ *:[i32] }:$RHi) 29269 …] }:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$RLo, GPR:{ *:[i32] }:$R… 29270 …*:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$Rn, ?:{ *:[i32] }:$Rm, ?:{ *:[i32] }:$RLo, ?:{ *:[i32] }:$RHi) [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrInfo.td | 3941 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3943 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3945 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3947 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3950 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 3953 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]> { 3965 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 3967 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3969 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3973 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), [all …]
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D | ARMInstrThumb2.td | 2586 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 2588 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">; 2592 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 2594 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">; 2598 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 2600 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 19373 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo); in LowerMUL() local 19375 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT)); in LowerMUL() 19377 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMUL() 19553 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo); in LowerMULH() local 19555 RLo = DAG.getNode(ISD::SRL, dl, ExVT, RLo, DAG.getConstant(8, dl, ExVT)); in LowerMULH() 19557 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMULH() 20285 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R); in LowerShift() local 20289 RLo = DAG.getBitcast(ExtVT, RLo); in LowerShift() 20293 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo, in LowerShift() 20297 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo); in LowerShift() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 22616 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo); in LowerMUL() local 22618 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT)); in LowerMUL() 22620 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMUL() 22830 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo); in LowerMULH() local 22832 RLo = DAG.getNode(ISD::SRL, dl, ExVT, RLo, DAG.getConstant(8, dl, ExVT)); in LowerMULH() 22834 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMULH() 23691 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R); in LowerShift() local 23695 RLo = DAG.getBitcast(ExtVT, RLo); in LowerShift() 23699 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo, in LowerShift() 23703 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo); in LowerShift() [all …]
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