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Searched refs:RegUnit (Results 1 – 25 of 36) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegisterPressure.cpp101 dbgs() << printVRegOrUnit(P.RegUnit, TRI); in dump()
109 dbgs() << printVRegOrUnit(P.RegUnit, TRI); in dump()
140 void RegPressureTracker::increaseRegPressure(unsigned RegUnit, in increaseRegPressure() argument
146 PSetIterator PSetI = MRI->getPressureSets(RegUnit); in increaseRegPressure()
155 void RegPressureTracker::decreaseRegPressure(unsigned RegUnit, in decreaseRegPressure() argument
158 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask); in decreaseRegPressure()
348 unsigned RegUnit = Pair.RegUnit; in initLiveThru() local
349 if (TargetRegisterInfo::isVirtualRegister(RegUnit) in initLiveThru()
350 && !RPTracker.hasUntiedDef(RegUnit)) in initLiveThru()
351 increaseSetPressure(LiveThruPressure, *MRI, RegUnit, in initLiveThru()
[all …]
DLiveRegMatrix.cpp179 unsigned RegUnit) { in query() argument
180 LiveIntervalUnion::Query &Q = Queries[RegUnit]; in query()
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
/external/llvm/lib/CodeGen/
DRegisterPressure.cpp75 dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); in dump()
83 dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); in dump()
112 void RegPressureTracker::increaseRegPressure(unsigned RegUnit, in increaseRegPressure() argument
118 PSetIterator PSetI = MRI->getPressureSets(RegUnit); in increaseRegPressure()
127 void RegPressureTracker::decreaseRegPressure(unsigned RegUnit, in decreaseRegPressure() argument
130 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask); in decreaseRegPressure()
322 unsigned RegUnit = Pair.RegUnit; in initLiveThru() local
323 if (TargetRegisterInfo::isVirtualRegister(RegUnit) in initLiveThru()
324 && !RPTracker.hasUntiedDef(RegUnit)) in initLiveThru()
325 increaseSetPressure(LiveThruPressure, *MRI, RegUnit, 0, Pair.LaneMask); in initLiveThru()
[all …]
DLiveRegMatrix.cpp172 unsigned RegUnit) { in query() argument
173 LiveIntervalUnion::Query &Q = Queries[RegUnit]; in query()
174 Q.init(UserTag, &VirtReg, &Matrix[RegUnit]); in query()
DMachineTraceMetrics.cpp681 unsigned RegUnit; member
686 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
688 LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {} in LiveRegUnit()
1120 TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle)); in computeInstrHeights()
1121 DEBUG(dbgs() << ' ' << PrintRegUnit(RI->RegUnit, MTM.TRI) in computeInstrHeights()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DRegisterPressure.h41 unsigned RegUnit; ///< Virtual register or register unit. member
44 RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask) in RegisterMaskPair()
45 : RegUnit(RegUnit), LaneMask(LaneMask) {} in RegisterMaskPair()
163 void addPressureChange(unsigned RegUnit, bool IsDec,
308 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
321 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
553 void increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
555 void decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
566 LaneBitmask getLastUsedLanes(unsigned RegUnit, SlotIndex Pos) const;
567 LaneBitmask getLiveLanesAt(unsigned RegUnit, SlotIndex Pos) const;
[all …]
DMachineRegisterInfo.h618 PSetIterator getPressureSets(unsigned RegUnit) const;
1158 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator() argument
1160 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) { in PSetIterator()
1161 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); in PSetIterator()
1166 PSet = TRI->getRegUnitPressureSets(RegUnit); in PSetIterator()
1167 Weight = TRI->getRegUnitWeight(RegUnit); in PSetIterator()
1188 getPressureSets(unsigned RegUnit) const { in getPressureSets() argument
1189 return PSetIterator(RegUnit, this); in getPressureSets()
DMachineTraceMetrics.h77 unsigned RegUnit; member
82 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
84 LiveRegUnit(unsigned RU) : RegUnit(RU) {} in LiveRegUnit()
DTargetRegisterInfo.h440 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { in hasRegUnit() argument
442 if (*Units == RegUnit) in hasRegUnit()
766 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
786 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
DLiveRegMatrix.h151 LiveIntervalUnion::Query &query(const LiveRange &LR, unsigned RegUnit);
/external/llvm/include/llvm/CodeGen/
DRegisterPressure.h30 unsigned RegUnit; ///< Virtual register or register unit. member
33 RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask) in RegisterMaskPair()
34 : RegUnit(RegUnit), LaneMask(LaneMask) {} in RegisterMaskPair()
146 void addPressureChange(unsigned RegUnit, bool IsDec,
288 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
301 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
538 void increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
540 void decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
551 LaneBitmask getLastUsedLanes(unsigned RegUnit, SlotIndex Pos) const;
552 LaneBitmask getLiveLanesAt(unsigned RegUnit, SlotIndex Pos) const;
[all …]
DMachineRegisterInfo.h564 PSetIterator getPressureSets(unsigned RegUnit) const;
1029 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator() argument
1031 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) { in PSetIterator()
1032 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); in PSetIterator()
1037 PSet = TRI->getRegUnitPressureSets(RegUnit); in PSetIterator()
1038 Weight = TRI->getRegUnitWeight(RegUnit); in PSetIterator()
1058 getPressureSets(unsigned RegUnit) const { in getPressureSets() argument
1059 return PSetIterator(RegUnit, this); in getPressureSets()
DLiveRegMatrix.h139 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned RegUnit);
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.h472 struct RegUnit { struct
490 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { in RegUnit() argument
541 SmallVector<RegUnit, 8> RegUnits;
665 RegUnit &RU = RegUnits.back();
693 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } in getRegUnit()
694 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } in getRegUnit()
/external/llvm/utils/TableGen/
DCodeGenRegisters.h435 struct RegUnit { struct
450 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { in RegUnit() function
499 SmallVector<RegUnit, 8> RegUnits;
646 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } in getRegUnit()
647 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } in getRegUnit()
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h617 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator() argument
618 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); in MCRegUnitRootIterator()
619 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
620 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCRegisterInfo.h648 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator() argument
649 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); in MCRegUnitRootIterator()
650 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
651 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DGCNRegPressure.cpp240 return RM.RegUnit == Reg; in collectVirtualRegUses()
321 auto LiveMask = LiveRegs[U.RegUnit]; in recede()
322 AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI); in recede()
344 auto &LiveMask = LiveRegs[U.RegUnit]; in recede()
347 CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI); in recede()
DSIWholeQuadMode.cpp283 for (MCRegUnitIterator RegUnit(Reg, TRI); RegUnit.isValid(); ++RegUnit) { in markInstructionUses() local
284 LiveRange &LR = LIS->getRegUnit(*RegUnit); in markInstructionUses()
DSIMachineScheduler.h476 InRegs.insert(RegMaskPair.RegUnit); in getInRegs()
484 OutRegs.insert(RegMaskPair.RegUnit); in getOutRegs()
DSIRegisterInfo.h223 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
DSIRegisterInfo.cpp1563 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const { in getRegUnitPressureSets()
1566 if (hasRegUnit(AMDGPU::M0, RegUnit)) in getRegUnitPressureSets()
1568 return AMDGPURegisterInfo::getRegUnitPressureSets(RegUnit); in getRegUnitPressureSets()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h429 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { in hasRegUnit() argument
431 if (*Units == RegUnit) in hasRegUnit()
723 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
743 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
/external/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.h465 InRegs.insert(RegMaskPair.RegUnit); in getInRegs()
DSIMachineScheduler.cpp331 if (TargetRegisterInfo::isVirtualRegister(RegMaskPair.RegUnit)) in initRegPressure()
332 LiveInRegs.insert(RegMaskPair.RegUnit); in initRegPressure()
358 unsigned Reg = RegMaskPair.RegUnit; in initRegPressure()

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