| /external/dng_sdk/source/ |
| D | dng_fingerprint.cpp | 466 S21 = 5, in MD5Transform() enumerator
530 GG (a, b, c, d, x[ 1], S21, 0xf61e2562); /* 17 */ in MD5Transform()
534 GG (a, b, c, d, x[ 5], S21, 0xd62f105d); /* 21 */ in MD5Transform()
538 GG (a, b, c, d, x[ 9], S21, 0x21e1cde6); /* 25 */ in MD5Transform()
542 GG (a, b, c, d, x[13], S21, 0xa9e3e905); /* 29 */ in MD5Transform()
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| /external/ppp/pppd/ |
| D | md5.c | 232 #define S21 5 macro
236 GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
240 GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
244 GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
248 GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
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| /external/bouncycastle/repackaged/bcprov/src/main/java/com/android/org/bouncycastle/crypto/digests/ |
| D | MD5Digest.java | 164 private static final int S21 = 5; field in MD5Digest
260 a = rotateLeft(a + G(b, c, d) + X[ 1] + 0xf61e2562, S21) + b; in processBlock()
264 a = rotateLeft(a + G(b, c, d) + X[ 5] + 0xd62f105d, S21) + b; in processBlock()
268 a = rotateLeft(a + G(b, c, d) + X[ 9] + 0x21e1cde6, S21) + b; in processBlock()
272 a = rotateLeft(a + G(b, c, d) + X[13] + 0xa9e3e905, S21) + b; in processBlock()
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| /external/bouncycastle/bcprov/src/main/java/org/bouncycastle/crypto/digests/ |
| D | MD5Digest.java | 162 private static final int S21 = 5; field in MD5Digest
258 a = rotateLeft(a + G(b, c, d) + X[ 1] + 0xf61e2562, S21) + b; in processBlock()
262 a = rotateLeft(a + G(b, c, d) + X[ 5] + 0xd62f105d, S21) + b; in processBlock()
266 a = rotateLeft(a + G(b, c, d) + X[ 9] + 0x21e1cde6, S21) + b; in processBlock()
270 a = rotateLeft(a + G(b, c, d) + X[13] + 0xa9e3e905, S21) + b; in processBlock()
|
| /external/clang/test/PCH/ |
| D | cxx-key-functions.cpp | 29 struct S21 { virtual void f(); }; struct
84 S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
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| /external/boringssl/src/crypto/poly1305/ |
| D | poly1305_vec.c | 65 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member
194 p->S21.v = _mm_mul_epu32(p->R21.v, FIVE); in poly1305_first_block()
265 T5 = _mm_mul_epu32(H4, p->S21.v); in poly1305_blocks()
323 T5 = _mm_mul_epu32(M4, p->S21.v); in poly1305_blocks()
462 T5 = _mm_mul_epu32(H4, p->S21.v); in poly1305_combine()
552 p->S21.d[2] = p->R21.d[2] * 5; in poly1305_combine()
575 T5 = _mm_mul_epu32(H4, p->S21.v); in poly1305_combine()
|
| /external/clang/test/CodeGenCXX/ |
| D | microsoft-abi-static-initializers.cpp | 80 static S S21; in MultipleStatics() local
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 177 case S21: case D21: return 21; in getARMRegisterNumbering()
|
| /external/clang/test/Misc/ |
| D | diag-template-diffing.cpp | 551 template<typename T> struct S21 {}; struct
552 template<typename T> using U21 = volatile S21<T>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCInstrFormats.td | 119 bits<21> S21; // 2-byte aligned 21-bit byte-offset.
121 let Inst{26-18} = S21{10-2};
122 let Inst{15-6} = S21{20-11};
138 let Inst{17} = S21{1};
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| D | ARCInstrInfo.td | 331 def Bcc : F32_BR0_COND<(outs), (ins btargetS21:$S21, ccond:$cc),
332 "b$cc\t$S21", []>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 84 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
103 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
|
| D | ARMCallingConv.td | 96 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
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| D | ARMBaseRegisterInfo.cpp | 715 case ARM::S21: return ARM::S20; in getRegisterPairEven()
768 case ARM::S20: return ARM::S21; in getRegisterPairOdd()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 58 case AArch64::S21: in isOdd()
|
| D | AArch64RegisterInfo.td | 325 def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>;
360 def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 58 case AArch64::S21: in isOdd()
|
| D | AArch64RegisterInfo.td | 306 def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>;
341 def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
|
| /external/protobuf/src/google/protobuf/stubs/ |
| D | structurally_valid.cc | 76 #define S21 (kExitReplace21) macro
338 #undef S21
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 91 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
110 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
|
| D | ARMCallingConv.td | 112 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 103 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
122 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
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| D | ARMCallingConv.td | 112 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 235 PPC::S20, PPC::S21, PPC::S22, PPC::S23,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 295 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
|