| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 725 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
752 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 863 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 926 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
953 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | Analysis.cpp | 165 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break; in getFCmpCondCode()
191 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 175 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
191 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
206 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 174 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
190 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
205 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 319 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: in Select()
337 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE: in Select()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | README.txt | 77 SETUGE unimplemented
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 68 IntRegs:$fval, SETUGE)),
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 53 defm GE_U : ComparisonInt<SETUGE, "ge_u">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 53 defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 243 case ISD::SETUGE: in softenSetCCOperands()
1578 case ISD::SETUGE: in SimplifySetCC()
1601 case ISD::SETUGE: in SimplifySetCC()
1748 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
1780 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
1876 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
1889 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
1963 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
2163 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInsertSkips.cpp | 230 case ISD::SETUGE: in kill()
|
| D | AMDGPUISelLowering.cpp | 1300 case ISD::SETUGE: in combineFMinMaxLegacy()
1665 ISD::SETUGE); in LowerUDIVREM64()
1667 ISD::SETUGE); in LowerUDIVREM64()
1687 ISD::SETUGE); in LowerUDIVREM64()
1689 ISD::SETUGE); in LowerUDIVREM64()
1747 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE); in LowerUDIVREM64()
1753 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
1826 ISD::SETUGE); in LowerUDIVREM()
1832 ISD::SETUGE); in LowerUDIVREM()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 248 case ISD::SETUGE: in softenSetCCOperands()
1899 } else if (Cond == ISD::CondCode::SETUGE) { in optimizeSetCCOfSignedTruncationCheck()
2173 case ISD::SETUGE: in SimplifySetCC()
2198 case ISD::SETUGE: in SimplifySetCC()
2355 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
2508 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
2521 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
2604 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
2800 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 1010 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGE),
1057 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGE),
1129 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGE)),
1150 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGE)),
1171 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGE)),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 552 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
565 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
578 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
591 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGE, SETOGE, "ge">;
600 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGE, SETOGE, "ge">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 1010 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGE),
1057 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGE),
1129 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGE)),
1150 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGE)),
1171 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGE)),
|
| D | PPCInstrInfo.td | 3274 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3505 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3533 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3573 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3601 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3629 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3660 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3691 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUGE)),
3725 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3752 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
[all …]
|
| D | PPCISelDAGToDAG.cpp | 2864 case ISD::SETUGE: in get32BitZExtCompare()
3037 case ISD::SETUGE: in get32BitSExtCompare()
3196 case ISD::SETUGE: in get64BitZExtCompare()
3359 case ISD::SETUGE: in get64BitSExtCompare()
3631 case ISD::SETUGE: in SelectCC()
3658 case ISD::SETUGE: in SelectCC()
3698 case ISD::SETUGE: in getPredicateForSetCC()
3722 case ISD::SETUGE: in getCRIdxForSetCC()
3755 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
3799 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2083 case ISD::SETUGE: in SimplifySetCC()
2106 case ISD::SETUGE: in SimplifySetCC()
2239 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
2257 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
2382 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
2567 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 778 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE),
815 (i32 GPR:$T), (i32 GPR:$F), SETUGE),
846 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE), bb:$T),
|
| D | MBlazeInstrFPU.td | 196 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGE),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 562 case ISD::SETUGE: in getPredicateForSetCC()
590 case ISD::SETUGE: in getCRIdxForSetCC()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 426 case ISD::SETUGE: in intCCToAVRCC()
509 CC = ISD::SETUGE; in getAVRCmp()
517 CC = ISD::SETUGE; in getAVRCmp()
|