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Searched refs:SRDS_PLLCR0_FRATE_SEL_MASK (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dfsl_corenet2_serdes.c238 switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) { in serdes_init()
Dfsl_corenet_serdes.c404 SRDS_PLLCR0_FRATE_SEL_MASK, in p4080_erratum_serdes8()
/external/u-boot/arch/arm/include/asm/arch-ls102xa/
Dimmap_ls102xa.h330 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 macro
/external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
Dimmap_lsch2.h560 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 macro
/external/u-boot/arch/powerpc/include/asm/
Dimmap_85xx.h2553 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 macro
2634 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 macro