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Searched refs:SignBit (Results 1 – 25 of 27) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/DebugInfo/DWARF/
DDWARFExpression.h45 SignBit = 0x8, enumerator
46 SignedSize1 = SignBit | Size1,
47 SignedSize2 = SignBit | Size2,
48 SignedSize4 = SignBit | Size4,
49 SignedSize8 = SignBit | Size8,
50 SignedSizeLEB = SignBit | SizeLEB,
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp186 SDValue SignBit = DAG.getNode(ISD::SHL, dl, RVT, DAG.getConstant(1, RVT), in SoftenFloatRes_FCOPYSIGN() local
189 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
194 SignBit = DAG.getNode(ISD::SRL, dl, RVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
196 TLI.getShiftAmountTy(SignBit.getValueType()))); in SoftenFloatRes_FCOPYSIGN()
197 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
199 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
200 SignBit = DAG.getNode(ISD::SHL, dl, LVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
202 TLI.getShiftAmountTy(SignBit.getValueType()))); in SoftenFloatRes_FCOPYSIGN()
213 return DAG.getNode(ISD::OR, dl, LVT, LHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
DLegalizeDAG.cpp1889 SDValue SignBit; in ExpandFCOPYSIGN() local
1894 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2); in ExpandFCOPYSIGN()
1907 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), in ExpandFCOPYSIGN()
1918 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), in ExpandFCOPYSIGN()
1925 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, in ExpandFCOPYSIGN()
1927 TLI.getShiftAmountTy(SignBit.getValueType()))); in ExpandFCOPYSIGN()
1931 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), in ExpandFCOPYSIGN()
1932 SignBit, DAG.getConstant(0, SignBit.getValueType()), in ExpandFCOPYSIGN()
1938 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, in ExpandFCOPYSIGN()
2475 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); in ExpandLegalINT_TO_FP() local
[all …]
DTargetLowering.cpp1577 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); in SimplifyDemandedBits() local
1581 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { in SimplifyDemandedBits()
1585 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. in SimplifyDemandedBits()
DSelectionDAG.cpp1807 APInt SignBit = APInt::getSignBit(BitWidth); in ComputeMaskedBits() local
1808 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. in ComputeMaskedBits()
1810 if (KnownZero.intersects(SignBit)) { in ComputeMaskedBits()
1812 } else if (KnownOne.intersects(SignBit)) { in ComputeMaskedBits()
DDAGCombiner.cpp5026 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); in visitBITCAST() local
5029 NewConv, DAG.getConstant(SignBit, VT)); in visitBITCAST()
5032 NewConv, DAG.getConstant(~SignBit, VT)); in visitBITCAST()
5065 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); in visitBITCAST() local
5067 X, DAG.getConstant(SignBit, VT)); in visitBITCAST()
5073 Cst, DAG.getConstant(~SignBit, VT)); in visitBITCAST()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/DebugInfo/DWARF/
DDWARFExpression.cpp127 unsigned Signed = Size & Operation::SignBit; in extract()
132 switch (Size & ~Operation::SignBit) { in extract()
242 unsigned Signed = Size & Operation::SignBit; in print()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp262 SDValue SignBit = DAG.getNode( in SoftenFloatRes_FCOPYSIGN() local
266 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
271 SignBit = in SoftenFloatRes_FCOPYSIGN()
272 DAG.getNode(ISD::SRL, dl, RVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
274 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
276 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
278 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
279 SignBit = in SoftenFloatRes_FCOPYSIGN()
280 DAG.getNode(ISD::SHL, dl, LVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
282 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
[all …]
DLegalizeDAG.cpp1359 uint8_t SignBit; member
1377 State.SignBit = NumBits - 1; in getSignAsIntValue()
1414 State.SignBit = 7; in getSignAsIntValue()
1444 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN() local
1453 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1467 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN()
1468 if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) { in ExpandFCOPYSIGN()
1471 SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1474 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1476 SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
[all …]
DTargetLowering.cpp836 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); in SimplifyDemandedBits() local
840 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { in SimplifyDemandedBits()
858 if (KnownOne.intersects(SignBit)) in SimplifyDemandedBits()
DDAGCombiner.cpp7476 SDValue SignBit = DAG.getConstant( in visitBITCAST() local
7480 FlipBit = SignBit; in visitBITCAST()
7489 FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit); in visitBITCAST()
7497 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); in visitBITCAST() local
7500 NewConv, DAG.getConstant(SignBit, DL, VT)); in visitBITCAST()
7503 NewConv, DAG.getConstant(~SignBit, DL, VT)); in visitBITCAST()
7545 APInt SignBit = APInt::getSignBit(VT.getSizeInBits() / 2); in visitBITCAST() local
7559 DAG.getConstant(SignBit, SDLoc(XorResult64), MVT::i64)); in visitBITCAST()
7566 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); in visitBITCAST() local
7568 X, DAG.getConstant(SignBit, SDLoc(X), VT)); in visitBITCAST()
[all …]
DSelectionDAG.cpp2198 APInt SignBit = APInt::getSignBit(BitWidth); in computeKnownBits() local
2199 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. in computeKnownBits()
2201 if (KnownZero.intersects(SignBit)) { in computeKnownBits()
2203 } else if (KnownOne.intersects(SignBit)) { in computeKnownBits()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp265 SDValue SignBit = DAG.getNode( in SoftenFloatRes_FCOPYSIGN() local
269 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
274 SignBit = in SoftenFloatRes_FCOPYSIGN()
275 DAG.getNode(ISD::SRL, dl, RVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
277 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
279 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
281 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
282 SignBit = in SoftenFloatRes_FCOPYSIGN()
283 DAG.getNode(ISD::SHL, dl, LVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
285 TLI.getShiftAmountTy(SignBit.getValueType(), in SoftenFloatRes_FCOPYSIGN()
[all …]
DLegalizeDAG.cpp71 uint8_t SignBit; member
1403 State.SignBit = NumBits - 1; in getSignAsIntValue()
1439 State.SignBit = 7; in getSignAsIntValue()
1468 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN() local
1477 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1491 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN()
1493 if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) { in ExpandFCOPYSIGN()
1494 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
1499 SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1502 SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
[all …]
DDAGCombiner.cpp9823 SDValue SignBit = DAG.getConstant( in visitBITCAST() local
9827 FlipBit = SignBit; in visitBITCAST()
9836 FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit); in visitBITCAST()
9844 APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); in visitBITCAST() local
9847 NewConv, DAG.getConstant(SignBit, DL, VT)); in visitBITCAST()
9850 NewConv, DAG.getConstant(~SignBit, DL, VT)); in visitBITCAST()
9892 APInt SignBit = APInt::getSignMask(VT.getSizeInBits() / 2); in visitBITCAST() local
9906 DAG.getConstant(SignBit, SDLoc(XorResult64), MVT::i64)); in visitBITCAST()
9913 APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); in visitBITCAST() local
9915 X, DAG.getConstant(SignBit, SDLoc(X), VT)); in visitBITCAST()
[all …]
/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp665 APInt SignBit(APInt::getSignBit(BitWidth)); in SimplifyDemandedUseBits() local
667 SignBit = APIntOps::lshr(SignBit, ShiftAmt); in SimplifyDemandedUseBits()
677 } else if ((KnownOne & SignBit) != 0) { // New bits are known one. in SimplifyDemandedUseBits()
DInstCombineCompares.cpp1052 const APInt &SignBit = XorCST->getValue(); in visitICmpInstWithInstAndIntCst() local
1058 RHSV ^ SignBit)); in visitICmpInstWithInstAndIntCst()
/external/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp655 APInt SignBit(APInt::getSignBit(BitWidth)); in SimplifyDemandedUseBits() local
657 SignBit = APIntOps::lshr(SignBit, ShiftAmt); in SimplifyDemandedUseBits()
668 } else if ((KnownOne & SignBit) != 0) { // New bits are known one. in SimplifyDemandedUseBits()
DInstCombineCompares.cpp1605 const APInt &SignBit = XorCst->getValue(); in visitICmpInstWithInstAndIntCst() local
1610 Builder->getInt(RHSV ^ SignBit)); in visitICmpInstWithInstAndIntCst()
/external/swiftshader/third_party/LLVM/lib/Support/
DAPInt.cpp1132 unsigned SignBit = APINT_BITS_PER_WORD - BitWidth; in ashr() local
1134 (((int64_t(VAL) << SignBit) >> SignBit) >> shiftAmt)); in ashr()
/external/llvm/lib/Support/
DAPInt.cpp1068 unsigned SignBit = APINT_BITS_PER_WORD - BitWidth; in ashr() local
1070 (((int64_t(VAL) << SignBit) >> SignBit) >> shiftAmt)); in ashr()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1664 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC() local
1667 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
1930 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64); in LowerINT_TO_FP32() local
1931 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp8103 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); in LowerFCOPYSIGN() local
8108 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); in LowerFCOPYSIGN()
8109 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, in LowerFCOPYSIGN()
8111 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); in LowerFCOPYSIGN()
8112 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, in LowerFCOPYSIGN()
8135 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); in LowerFCOPYSIGN()
8573 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), in LowerVSETCC() local
8575 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); in LowerVSETCC()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp2014 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC() local
2017 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
2325 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64); in LowerINT_TO_FP32() local
2326 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp330 MachineSDNode *flipSignBit(const SDValue &N, SDNode **SignBit = nullptr);

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