Searched refs:SrcReg0Sub0 (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2715 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp() local
2724 .addOperand(SrcReg0Sub0); in splitScalar64BitUnaryOp()
2774 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp() local
2785 .addOperand(SrcReg0Sub0) in splitScalar64BitBinaryOp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4195 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp() local
4203 BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp()
4252 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitAddSub() local
4267 .add(SrcReg0Sub0) in splitScalar64BitAddSub()
4320 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp() local
4331 .add(SrcReg0Sub0) in splitScalar64BitBinaryOp()
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