| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 276 MachineInstrBuilder MachineIRBuilderBase::buildBrCond(unsigned Tst, in buildBrCond() argument
278 assert(getMRI()->getType(Tst).isScalar() && "invalid operand type"); in buildBrCond()
280 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); in buildBrCond()
606 unsigned Tst, in buildSelect() argument
616 assert(getMRI()->getType(Tst).isScalar() && "type mismatch"); in buildSelect()
618 assert((getMRI()->getType(Tst).isScalar() || in buildSelect()
619 (getMRI()->getType(Tst).isVector() && in buildSelect()
620 getMRI()->getType(Tst).getNumElements() == in buildSelect()
627 .addUse(Tst) in buildSelect()
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| D | IRTranslator.cpp | 341 unsigned Tst = getOrCreateVReg(*BrInst.getCondition()); in translateBr() local
344 MIRBuilder.buildBrCond(Tst, TrueBB); in translateBr()
377 const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1); in translateSwitch() local
378 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue); in translateSwitch()
383 MIRBuilder.buildBrCond(Tst, TrueMBB); in translateSwitch()
542 unsigned Tst = getOrCreateVReg(*U.getOperand(0)); in translateSelect() local
548 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i]); in translateSelect()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 441 MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
693 MachineInstrBuilder buildSelect(unsigned Res, unsigned Tst,
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| /external/v8/src/arm64/ |
| D | deoptimizer-arm64.cc | 155 __ Tst(x1, kSmiTagMask); in Generate() local
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| D | macro-assembler-arm64.cc | 1401 Tst(temp, 15); in AssertSpAligned()
1499 Tst(fpcr, RMode_mask); in AssertFPCRState()
1568 Tst(object, kSmiTagMask); in AssertSmi()
1576 Tst(object, kSmiTagMask); in AssertNotSmi()
1590 Tst(temp, Operand(Map::IsConstructorBit::kMask)); in AssertConstructor()
2558 Tst(x1, x1); in MaybeDropFrames()
2765 Tst(scratch, kPointerSize - 1); in RecordWriteField()
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| D | macro-assembler-arm64-inl.h | 41 void TurboAssembler::Tst(const Register& rn, const Operand& operand) { in Tst() function
1321 Tst(reg, bit_pattern); in TestAndBranchIfAnySet()
1334 Tst(reg, bit_pattern); in TestAndBranchIfAllClear()
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| D | macro-assembler-arm64.h | 627 inline void Tst(const Register& rn, const Operand& operand);
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| /external/vixl/test/aarch32/ |
| D | test-simulator-cond-rd-operand-const-a32.cc | 123 M(Tst)
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| D | test-simulator-cond-rd-operand-const-t32.cc | 123 M(Tst)
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| D | test-simulator-cond-rd-operand-rn-t32.cc | 123 M(Tst) \
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| D | test-simulator-cond-rd-operand-rn-a32.cc | 123 M(Tst) \
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| D | test-disasm-a32.cc | 2353 TEST_SHIFT_T32(Tst, "tst", 0x0000000a) in TEST()
2370 TEST_WIDE_IMMEDIATE(Tst, "tst", 0x0000000e); in TEST()
2373 TEST_WIDE_IMMEDIATE_PC(Tst, "tst", 0x0000000e); in TEST()
3674 COMPARE_T32(Tst(eq, r0, r1), in TEST()
3678 COMPARE_T32(Tst(eq, r8, r9), in TEST()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 123 M(Tst)
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 123 M(Tst)
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 123 M(Tst)
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 123 M(Tst)
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| D | test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 123 M(Tst)
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| /external/honggfuzz/examples/apache-httpd/corpus_http2/ |
| D | e00bd26115de24b8a11e493be5c0ab62.00001d13.honggfuzz.cov | 41 �'1����Vo�$�'�@������S�,�h4�5��M !;;@��=b�S ��A||�zd�U�����pK�}TstmN��\Ms�4ˬb�X�؎��f8�…
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| D | 58f675a3f9e4d017bdeb861e34d613b1.0000604c.honggfuzz.cov | 48 �'1����Vo�$�'�@������S�,�h4�5��M !;;@��=b�S ��A||�zd�U�����pK�}TstmN��\Ms�4ˬb�X�؎��f8�…
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| /external/v8/src/builtins/arm64/ |
| D | builtins-arm64.cc | 50 __ Tst(x10, kSmiTagMask); in Generate_InternalArrayConstructor() local
701 __ Tst(args_size, kPointerSize - 1); in LeaveInterpreterFrame() local
840 __ Tst(bytecode, Operand(0x1)); in AdvanceBytecodeOffsetOrReturn() local
2988 __ Tst(result, kXSignMask); in Generate_DoubleToI() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 423 Tst, enumerator
1068 using InstARM32Tst = InstARM32CmpLike<InstARM32::Tst>;
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| D | IceInstARM32.cpp | 3539 template class InstARM32CmpLike<InstARM32::Tst>;
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1289 __ Tst(i.InputOrZeroRegister64(0), i.InputOperand2_64(1)); in AssembleArchInstruction() local
1292 __ Tst(i.InputOrZeroRegister32(0), i.InputOperand2_32(1)); in AssembleArchInstruction() local
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 746 void MacroAssembler::Tst(const Register& rn, const Operand& operand) { in Tst() function in vixl::aarch64::MacroAssembler
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| D | macro-assembler-aarch64.h | 659 void Tst(const Register& rn, const Operand& operand);
|