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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSelectionDAGNodes.h1584 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
1587 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
1769 Ld->getAddressingMode() == ISD::UNINDEXED;
1804 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
1812 St->getAddressingMode() == ISD::UNINDEXED;
1831 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
DISDOpcodes.h672 UNINDEXED = 0, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h808 UNINDEXED = 0, enumerator
DSelectionDAGNodes.h1798 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
1801 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2085 Ld->getAddressingMode() == ISD::UNINDEXED;
2115 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2123 St->getAddressingMode() == ISD::UNINDEXED;
2139 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h869 UNINDEXED = 0, enumerator
DSelectionDAGNodes.h2036 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2039 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2351 Ld->getAddressingMode() == ISD::UNINDEXED;
2381 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2389 St->getAddressingMode() == ISD::UNINDEXED;
2405 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
DBasicTTIImpl.h117 return ISD::UNINDEXED; in getISDIndexedMode()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp523 if (AM != ISD::UNINDEXED) { in SelectLoad()
631 if (AM != ISD::UNINDEXED) { in SelectStore()
673 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()
702 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp5105 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
5138 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
5146 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
5157 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
5166 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
5218 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(), in getStore()
5227 ISD::UNINDEXED, false, VT, MMO); in getStore()
5288 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(), in getTruncStore()
5297 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()
5341 ID.AddInteger(encodeMemSDNodeFlags(ExtTy, ISD::UNINDEXED, in getMaskedLoad()
[all …]
DLegalizeVectorTypes.cpp226 SDValue Result = DAG.getLoad(ISD::UNINDEXED, in ScalarizeVecRes_LOAD()
1063 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1070 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
DTargetLowering.cpp3245 assert(LD->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedLoad()
3402 assert(ST->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedStore()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp4188 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
4218 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
4228 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
4284 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(), in getStore()
4291 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, in getStore()
4351 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(), in getTruncStore()
4358 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED, in getTruncStore()
5659 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(), in MemSDNode()
5672 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(), in MemSDNode()
DLegalizeVectorTypes.cpp188 SDValue Result = DAG.getLoad(ISD::UNINDEXED, in ScalarizeVecRes_LOAD()
720 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
727 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp6272 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
6306 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
6313 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
6324 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, PtrInfo, in getExtLoad()
6332 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
6384 dl.getIROrder(), VTs, ISD::UNINDEXED, false, VT, MMO)); in getStore()
6392 ISD::UNINDEXED, false, VT, MMO); in getStore()
6451 dl.getIROrder(), VTs, ISD::UNINDEXED, true, SVT, MMO)); in getTruncStore()
6459 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()
DLegalizeVectorTypes.cpp225 ISD::UNINDEXED, N->getExtensionType(), in ScalarizeVecRes_LOAD()
1213 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1218 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetSelectionDAG.td596 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
661 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrFragmentsSIMD.td318 ST->getAddressingMode() == ISD::UNINDEXED &&
DX86ISelDAGToDAG.cpp404 LD->getAddressingMode() != ISD::UNINDEXED || in isCalleeLoad()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td709 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
819 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp454 if (AM != ISD::UNINDEXED) { in SelectLoad()
564 if (AM != ISD::UNINDEXED) { in SelectStore()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td645 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
646 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td246 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
328 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelDAGToDAG.cpp1332 if (AM == ISD::UNINDEXED) in SelectARMIndexedLoad()
1405 if (AM == ISD::UNINDEXED) in SelectT2IndexedLoad()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp563 assert( LN->getAddressingMode() == ISD::UNINDEXED in LowerLOAD()
776 assert( SN->getAddressingMode() == ISD::UNINDEXED in LowerSTORE()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1474 if (AM == ISD::UNINDEXED) in tryARMIndexedLoad()
1549 if (AM == ISD::UNINDEXED) in tryT2IndexedLoad()

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