Searched refs:USIR1 (Results 1 – 2 of 2) sorted by relevance
40 writel(readl(USIR1) | mask, USIR1); in udc_ack_int_UDCCR()412 if (readl(USIR1) & UDCCR_SUSIR) { in udc_irq()420 if (readl(USIR1) & UDCCR_RESIR) { in udc_irq()426 if (readl(USIR1) & (1<<31)) { in udc_irq()432 if (readl(USIR1) & UDCCR_RSTIR) { in udc_irq()
598 #define USIR1 0x40600010 /* UDC Status Interrupt Register 1 */ macro